`timescale 1ns / 100ps

module edge_detector (
    input clk,
    input reset,
    input update,
    input [1:0] level,
    output tick
    );

    localparam  s0 = 2'b00,
                s2 = 2'b10,
                s1 = 2'b01;



    reg [1:0] cur_state;
    reg [1:0] next_state;
    reg prev_update;

    always @(posedge clk)
    begin
            cur_state <= next_state;
            prev_update <= update;
    end

    always @(*)
    begin
        if(reset) next_state = s0;
        if (update && update != prev_update)
        begin
            case(cur_state)
                s0: next_state = s1;
                s2: next_state = (level==1)?s0:s1;
                s1: next_state = s2;
                default:next_state = s0;
            endcase
        end
    end

    assign tick = (cur_state == s2);
endmodule