alu

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ALU is
	port(
	OP_CODE: in STD_LOGIC_VECTOR(3 downto 0); --wejscie instrukcji
	SRC_1: in STD_LOGIC_VECTOR(7 downto 0); -- wejscie 1
	SRC_2: in STD_LOGIC_VECTOR(7 downto 0); -- wejscie 2
	SRC_AC: in STD_LOGIC; -- pomocnicze przeniesienie
	SRC_C: in STD_LOGIC; -- przeniesienie
	RST: in STD_LOGIC; -- reset

	DES_1: out STD_LOGIC_VECTOR(7 downto 0); -- wyjscie 1
	DES_2: out STD_LOGIC_VECTOR(7 downto 0); -- wyjscie 2
	DES_P: out STD_LOGIC; -- bit parzystosci
	DES_C: out STD_LOGIC; -- bit przeniesienia
	DES_AC: out STD_LOGIC; -- pomocnicze przeniesienie
	DES_OV: out STD_LOGIC -- bit przepelnienia

	);

end ALU;

architecture behaviour of ALU is

signal bufor: STD_LOGIC_VECTOR (8 downto 0); --dodatkowa zmienna
signal bufor2: STD_LOGIC_VECTOR (7 downto 0);
signal wynik: STD_LOGIC_VECTOR(15 downto 0);

begin

	process(RST) is

	variable t: std_logic_vector(6 downto 0):="0000000";

	begin

	if (RST'event and RST='0') then

		case OP_CODE is

			when "0000" => DES_1 <= std_logic_vector(unsigned(SRC_1) + unsigned(SRC_2)); --dodawanie

				bufor <= std_logic_vector(unsigned('0' & SRC_1) + unsigned('0' & SRC_2));
				if (unsigned(bufor))>"11111111" then
					DES_C <= '1'; --flaga przeniesienia
				else
					DES_C <='0';
				end if;

			when "0001" => bufor2 <= std_logic_vector(unsigned(SRC_1) + unsigned(SRC_2)); --dodawanie z przenies...
								DES_1 <=  std_logic_vector(unsigned(bufor2) + unsigned(t & SRC_C));

				bufor <= std_logic_vector(unsigned('0' & SRC_1) + unsigned('0' & SRC_2));
				bufor <= std_logic_vector(unsigned('0' & SRC_1) + unsigned(t & SRC_C));
				if (unsigned(bufor))>"11111111" then
					DES_C <= '1'; --flaga przeniesienia
				else
					DES_C <='0';
				end if;

			when "0010" => DES_1 <= std_logic_vector(unsigned(SRC_1) - unsigned(SRC_2) - unsigned(t & SRC_C)); --odejmowanie, co z flagami?

			when "0011" => DES_1 <= std_logic_vector(unsigned(SRC_1) + unsigned(t & '1'));

			when "0100" => DES_1 <= std_logic_vector(unsigned(SRC_1) - unsigned(t & '1'));

			when "0101" => wynik <= std_logic_vector(unsigned(SRC_1) * unsigned(SRC_2)); --mnozenie

				if (unsigned(wynik)) > "0000000011111111" then
					DES_OV <= '1';
				else
					DES_OV <= '0';
				end if;

					DES_1 <= wynik(7 downto 0);
					DES_2 <= wynik(15 downto 8);


			--when "0110" --dzielenie

			when "0111" => DES_1 <= SRC_1 AND SRC_2; --AND logiczny

			when "1000" => DES_1 <= SRC_1 OR SRC_2; --OR logiczny

			when "1001" => DES_1 <= SRC_1 XOR SRC_2; -- XOR/EXOR

			when "1010" => DES_1 <= NOT SRC_1; --negacja akumulatora

			when "1011" => DES_1 <= SRC_1(6 downto 0) & SRC_1(7);-- przesuniecie aku w lewo

			when "1100" => DES_1 <= SRC_1(6 downto 0) & SRC_C;-- w lewo ze znacznikiem Carry
								DES_C <= SRC_1(7);

			when "1101" => DES_1 <= SRC_1(0) & SRC_1(7 downto 1);-- przes. w prawo

			when "1110" => DES_1 <= SRC_C & SRC_1(7 downto 1);-- w prawo ze znacznikiem carry
								DES_C <= SRC_1(0);

			when "1111" => DES_1 <= SRC_1(3 downto 0) & SRC_1(7 downto 4);-- wymiana polbajtow - 4 razy przesuniecie (SWAP)

			when others => NULL;

		end case;

		end if;

	 end process;

end behaviour;