SetupSamplingTimer()
{
	//Init clock
	RCC->APB2ENR |= RCC_APB2ENR_TIM8EN;
	//Main sampling timer
	TIM1->DIER = 0;
	TIM1->SR &= ~TIM_SR_UIF;
	TIM1->CNT = 0;
	TIM1->PSC = 0;
	TIM1->CR1 = TIM_CR1_URS;
	TIM1->ARR = period;		//1Mhz clock it should be
	TIM1->CR2 = 0;
	TIM1->DIER = TIM_DIER_UDE;
	TIM1->EGR = TIM_EGR_UG;
}

SetupSamplingDMA(void *dataBuffer, uint32_t dataTransferCount)
{
	RCC_AHB1PeriphClockCmd(RCC_AHB1ENR_DMA2EN, ENABLE);

	//TIM1_UP -> DMA2, Ch6, Stream5
	//DMA should be stopped before this point
	DMA2_Stream5->CR = (DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2) | DMA_PDATAALIGN_BYTE | DMA_SxCR_MINC | DMA_SxCR_CIRC;
	DMA2_Stream5->M0AR = (uint32_t)dataBuffer;//samplingRam;
	DMA2_Stream5->PAR  = (uint32_t)&(SAMPLING_PORT->IDR);
	DMA2_Stream5->NDTR = dataTransferCount;	//transferCount->512
	DMA2_Stream5->FCR = DMA_SxFCR_DMDIS | DMA_SxFCR_FTH;
}

//Start DMA & Timer
DMA2->HIFCR = DMA_HIFCR_CTCIF5;
DMA2_Stream5->CR |= DMA_SxCR_EN;
TIM1->CR1 |= TIM_CR1_CEN;