RCA Synthesis

Release 14.5 - xst P.58f (nt64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.17 secs

--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.17 secs

--> Reading design: RCAdd_Sub.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "RCAdd_Sub.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "RCAdd_Sub"
Output Format                      : NGC
Target Device                      : xc3s250e-4-tq144

---- Source Options
Top Module Name                    : RCAdd_Sub
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 24
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Users/Alessandro/Desktop/ASE/RCA_substractor-generic/full_adder.vhd" in Library work.
Architecture dataflow of Entity full_adder is up to date.
Compiling vhdl file "C:/Users/Alessandro/Desktop/ASE/xor-generic/xor-generic.vhd" in Library work.
Architecture behavioural of Entity xor_generic is up to date.
Compiling vhdl file "C:/Users/Alessandro/Desktop/ASE/RCA-generic/RCA.vhd" in Library work.
Architecture structural of Entity rca is up to date.
Compiling vhdl file "C:/Users/Alessandro/Desktop/ASE/RCA_substractor-generic/RCAdd-Sub.vhd" in Library work.
Architecture structural of Entity rcadd_sub is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <RCAdd_Sub> in library <work> (architecture <structural>) with generics.
	N = 8

Analyzing hierarchy for entity <xor_generic> in library <work> (architecture <behavioural>) with generics.
	N = 8

Analyzing hierarchy for entity <RCA> in library <work> (architecture <structural>) with generics.
	N = 8

Analyzing hierarchy for entity <full_adder> in library <work> (architecture <dataflow>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing generic Entity <RCAdd_Sub> in library <work> (Architecture <structural>).
	N = 8
Entity <RCAdd_Sub> analyzed. Unit <RCAdd_Sub> generated.

Analyzing generic Entity <xor_generic> in library <work> (Architecture <behavioural>).
	N = 8
Entity <xor_generic> analyzed. Unit <xor_generic> generated.

Analyzing generic Entity <RCA> in library <work> (Architecture <structural>).
	N = 8
Entity <RCA> analyzed. Unit <RCA> generated.

Analyzing Entity <full_adder> in library <work> (Architecture <dataflow>).
Entity <full_adder> analyzed. Unit <full_adder> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <xor_generic>.
    Related source file is "C:/Users/Alessandro/Desktop/ASE/xor-generic/xor-generic.vhd".
    Found 8-bit xor2 for signal <s>.
Unit <xor_generic> synthesized.


Synthesizing Unit <full_adder>.
    Related source file is "C:/Users/Alessandro/Desktop/ASE/RCA_substractor-generic/full_adder.vhd".
    Found 1-bit xor2 for signal <s>.
    Found 1-bit xor2 for signal <c_out$xor0000> created at line 45.
Unit <full_adder> synthesized.


Synthesizing Unit <RCA>.
    Related source file is "C:/Users/Alessandro/Desktop/ASE/RCA-generic/RCA.vhd".
    Found 1-bit xor2 for signal <v>.
Unit <RCA> synthesized.


Synthesizing Unit <RCAdd_Sub>.
    Related source file is "C:/Users/Alessandro/Desktop/ASE/RCA_substractor-generic/RCAdd-Sub.vhd".
WARNING:Xst:1780 - Signal <carry_temp> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <RCAdd_Sub> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Xors                                                 : 25
 1-bit xor2                                            : 25

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Xors                                                 : 25
 1-bit xor2                                            : 25

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <RCAdd_Sub> ...

Optimizing unit <RCA> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block RCAdd_Sub, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : RCAdd_Sub.ngr
Top Level Output File Name         : RCAdd_Sub
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No

Design Statistics
# IOs                              : 27

Cell Usage :
# BELS                             : 17
#      LUT2                        : 1
#      LUT3                        : 1
#      LUT4                        : 15
# IO Buffers                       : 27
#      IBUF                        : 17
#      OBUF                        : 10
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s250etq144-4

 Number of Slices:                       10  out of   2448     0%
 Number of 4 input LUTs:                 17  out of   4896     0%
 Number of IOs:                          27
 Number of bonded IOBs:                  27  out of    108    25%

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
No clock signals found in this design

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 15.209ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 155 / 10
-------------------------------------------------------------------------
Delay:               15.209ns (Levels of Logic = 10)
  Source:            subtract (PAD)
  Destination:       overflow (PAD)

  Data Path: subtract to overflow
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            16   1.218   1.069  subtract_IBUF (subtract_IBUF)
     LUT3:I2->O            2   0.704   0.482  RCA_inst/f0_7[0].full_adder_instance/c_out1 (RCA_inst/carry<1>)
     LUT4:I2->O            2   0.704   0.482  RCA_inst/f0_7[1].full_adder_instance/c_out1 (RCA_inst/carry<2>)
     LUT4:I2->O            2   0.704   0.482  RCA_inst/f0_7[2].full_adder_instance/c_out1 (RCA_inst/carry<3>)
     LUT4:I2->O            2   0.704   0.482  RCA_inst/f0_7[3].full_adder_instance/c_out1 (RCA_inst/carry<4>)
     LUT4:I2->O            2   0.704   0.482  RCA_inst/f0_7[4].full_adder_instance/c_out1 (RCA_inst/carry<5>)
     LUT4:I2->O            2   0.704   0.482  RCA_inst/f0_7[5].full_adder_instance/c_out1 (RCA_inst/carry<6>)
     LUT4:I2->O            3   0.704   0.706  RCA_inst/f0_7[6].full_adder_instance/c_out1 (RCA_inst/carry<7>)
     LUT4:I0->O            1   0.704   0.420  RCA_inst/Mxor_v_Result1 (overflow_OBUF)
     OBUF:I->O                 3.272          overflow_OBUF (overflow)
    ----------------------------------------
    Total                     15.209ns (10.122ns logic, 5.087ns route)
                                       (66.6% logic, 33.4% route)

=========================================================================


Total REAL time to Xst completion: 10.00 secs
Total CPU time to Xst completion: 10.11 secs

-->

Total memory usage is 253932 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)