time_management

module time_manager(input clk,
        input rst,
        input [2:0] op,
        output [15:0]time_manager);

`define IDLE 3'b000
`define START 3'b001
`define STOP 3'b010
`define RESTART 3'b100

reg [15:0] cnt_reg, cnt_nxt;
reg [2:0] state_reg, state_nxt;
reg restart_flg_nxt;

always @(posedge clk or negedge rst)
    begin
        if(rst == 0)
        begin
            cnt_reg <= 0;
            state_reg <= 3'b000;
        end
        else
        begin
            cnt_reg <= cnt_nxt;
            state_reg <= state_nxt;
        end
    end
/*
always @*
begin
    cnt_nxt = cnt_reg + 1;
end*/




always @(cnt_reg, op, state_reg)
begin
state_nxt = state_reg;
restart_flg_nxt = 0;
case (state_reg)
    `IDLE:
        begin
           if(op == 3'b001)
            state_nxt = `START;
        end
    `START:
        begin
           cnt_nxt = cnt_reg + 1;
           if(restart_flg_nxt == 1)
            begin
                restart_flg_nxt=0;
                cnt_reg = 0;
                state_reg = `IDLE;
            end
           if(op == 3'b000)
            state_nxt = `IDLE;
           if(op == 3'b010)
            state_nxt = `STOP;
           if(op == 3'b100)
            state_nxt = `RESTART;
        end
    `STOP:
        begin
           if(op == 3'b001)
                state_nxt = `START;
        end
    `RESTART:
        begin
           restart_flg_nxt = 1;
           if(op == 3'b001)
            state_nxt = `START;
        end
endcase
end

assign time_manager = cnt_reg;

endmodule