module cau4_1_tb();
reg clk;
reg reset_n;
wire[6:0] h7 ;
wire[6:0] h6 ;
wire[6:0] h5 ;
wire[6:0] h4 ;
wire[6:0] h3 ;
wire[6:0] h2 ;
wire[6:0] h1 ;
wire[6:0] h0 ;

cau4_1 inst(
.clk(clk),
.reset_n(reset_n),
.h7 (h7),
.h6 (h6),
.h5 (h5),
.h4 (h4),
.h3 (h3),
.h2 (h2),
.h1 (h1),
.h0 (h0)
);

//init
initial begin
  $display("\ttime\tclk\trst\thex7\thex6\thex5\thex4\thex3\thex2\thex1\thex0");
  $monitor("%d\t%d\t%d\t%b\t%b\t%b\t%b\t%b\t%b\t%b\t%b", $time,clk,reset_n,h7,h6,h5,h4,h3,h2,h1,h0);
    clk = 1;
    reset_n = 1;
    #2 reset_n = 0;
    #2 reset_n = 1;
    #50 reset_n = 0;
end
//generate clk
always begin
 #1 clk = ~clk;
end
endmodule