diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index 2fa220a9..e5d87de7 100644
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -88,10 +88,9 @@ class RocketRV64(CPU):
         self.mem_axi   =  mem_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
         self.mmio_axi  = mmio_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4)

-        self.mem_wb    =  mem_wb = wishbone.Interface(data_width=64, adr_width=29)
         self.mmio_wb   = mmio_wb = wishbone.Interface(data_width=64, adr_width=29)

-        self.buses     = [mem_wb, mmio_wb]
+        self.buses     = [mmio_wb]

         # # #

@@ -207,14 +206,12 @@ class RocketRV64(CPU):
         )

         # adapt axi interfaces to wishbone
-        mem_a2w  = ResetInserter()(axi.AXI2Wishbone(mem_axi, mem_wb, base_address=0))
         mmio_a2w = ResetInserter()(axi.AXI2Wishbone(mmio_axi, mmio_wb, base_address=0))
         # NOTE: AXI2Wishbone FSMs must be reset with the CPU!
         self.comb += [
-            mem_a2w.reset.eq( ResetSignal() | self.reset),
             mmio_a2w.reset.eq(ResetSignal() | self.reset),
         ]
-        self.submodules += mem_a2w, mmio_a2w
+        self.submodules += mmio_a2w

         # add verilog sources
         self.add_sources(platform, variant)
diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index b373c834..c5dc0daa 100644
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -11,6 +11,7 @@ from litex.soc.interconnect import wishbone
 from litex.soc.integration.soc_core import *

 from litedram.frontend.wishbone import *
+from litedram.frontend.axi import *
 from litedram.core import LiteDRAMCore

 __all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
@@ -53,7 +54,7 @@ class SoCSDRAM(SoCCore):
             **kwargs)

         # SoC <--> L2 Cache <--> LiteDRAM ----------------------------------------------------------
-        if self.with_wishbone:
+        if False and self.with_wishbone:
             # LiteDRAM port ------------------------------------------------------------------------
             port = self.sdram.crossbar.get_port()
             port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2
@@ -86,6 +87,27 @@ class SoCSDRAM(SoCCore):

             # L2 Cache <--> LiteDRAM bridge --------------------------------------------------------
             self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port)
+        else:
+            # LiteDRAM port ------------------------------------------------------------------------
+            port = self.sdram.crossbar.get_port()
+            port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2
+
+            # Parameters ---------------------------------------------------------------------------
+            main_ram_size = 2**(geom_settings.bankbits +
+                                geom_settings.rowbits +
+                                geom_settings.colbits)*phy.settings.databits//8
+            main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now
+
+            # SoC <--> L2 Cache Wishbone interface -------------------------------------------------
+            # FIXME: we do this here just so that we get MAIN_RAM_BASE in the generated .h file!!!
+            # FIXME: we don't actually *use* the resulting self._wb_sdram interface!!!
+            wb_sdram = wishbone.Interface()
+            self.add_wb_sdram_if(wb_sdram)
+            self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size)
+
+            # LiteDRAM AXI port --------------------------------------------------------------------
+            axi2native = LiteDRAMAXI2Native(self.cpu.mem_axi, port)
+            self.submodules += axi2native

     def do_finalize(self):
         if not self.integrated_main_ram_size: