Guest User

Untitled

a guest
Oct 11th, 2019
223
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
  1. diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
  2. index 2fa220a9..e5d87de7 100644
  3. --- a/litex/soc/cores/cpu/rocket/core.py
  4. +++ b/litex/soc/cores/cpu/rocket/core.py
  5. @@ -88,10 +88,9 @@ class RocketRV64(CPU):
  6.          self.mem_axi   =  mem_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
  7.          self.mmio_axi  = mmio_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
  8.  
  9. -        self.mem_wb    =  mem_wb = wishbone.Interface(data_width=64, adr_width=29)
  10.          self.mmio_wb   = mmio_wb = wishbone.Interface(data_width=64, adr_width=29)
  11.  
  12. -        self.buses     = [mem_wb, mmio_wb]
  13. +        self.buses     = [mmio_wb]
  14.  
  15.          # # #
  16.  
  17. @@ -207,14 +206,12 @@ class RocketRV64(CPU):
  18.          )
  19.  
  20.          # adapt axi interfaces to wishbone
  21. -        mem_a2w  = ResetInserter()(axi.AXI2Wishbone(mem_axi, mem_wb, base_address=0))
  22.          mmio_a2w = ResetInserter()(axi.AXI2Wishbone(mmio_axi, mmio_wb, base_address=0))
  23.          # NOTE: AXI2Wishbone FSMs must be reset with the CPU!
  24.          self.comb += [
  25. -            mem_a2w.reset.eq( ResetSignal() | self.reset),
  26.              mmio_a2w.reset.eq(ResetSignal() | self.reset),
  27.          ]
  28. -        self.submodules += mem_a2w, mmio_a2w
  29. +        self.submodules += mmio_a2w
  30.  
  31.          # add verilog sources
  32.          self.add_sources(platform, variant)
  33. diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
  34. index b373c834..c5dc0daa 100644
  35. --- a/litex/soc/integration/soc_sdram.py
  36. +++ b/litex/soc/integration/soc_sdram.py
  37. @@ -11,6 +11,7 @@ from litex.soc.interconnect import wishbone
  38.  from litex.soc.integration.soc_core import *
  39.  
  40.  from litedram.frontend.wishbone import *
  41. +from litedram.frontend.axi import *
  42.  from litedram.core import LiteDRAMCore
  43.  
  44.  __all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
  45. @@ -53,7 +54,7 @@ class SoCSDRAM(SoCCore):
  46.              **kwargs)
  47.  
  48.          # SoC <--> L2 Cache <--> LiteDRAM ----------------------------------------------------------
  49. -        if self.with_wishbone:
  50. +        if False and self.with_wishbone:
  51.              # LiteDRAM port ------------------------------------------------------------------------
  52.              port = self.sdram.crossbar.get_port()
  53.              port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2
  54. @@ -86,6 +87,27 @@ class SoCSDRAM(SoCCore):
  55.  
  56.              # L2 Cache <--> LiteDRAM bridge --------------------------------------------------------
  57.              self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port)
  58. +        else:
  59. +            # LiteDRAM port ------------------------------------------------------------------------
  60. +            port = self.sdram.crossbar.get_port()
  61. +            port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2
  62. +
  63. +            # Parameters ---------------------------------------------------------------------------
  64. +            main_ram_size = 2**(geom_settings.bankbits +
  65. +                                geom_settings.rowbits +
  66. +                                geom_settings.colbits)*phy.settings.databits//8
  67. +            main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now
  68. +
  69. +            # SoC <--> L2 Cache Wishbone interface -------------------------------------------------
  70. +            # FIXME: we do this here just so that we get MAIN_RAM_BASE in the generated .h file!!!
  71. +            # FIXME: we don't actually *use* the resulting self._wb_sdram interface!!!
  72. +            wb_sdram = wishbone.Interface()
  73. +            self.add_wb_sdram_if(wb_sdram)
  74. +            self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size)
  75. +
  76. +            # LiteDRAM AXI port --------------------------------------------------------------------
  77. +            axi2native = LiteDRAMAXI2Native(self.cpu.mem_axi, port)
  78. +            self.submodules += axi2native
  79.  
  80.      def do_finalize(self):
  81.          if not self.integrated_main_ram_size:
RAW Paste Data