`define SPACE 0
`define DOT 1
`define SCORE 2
`define UNDERSCORE 3
`define COLON 4
`define A 15
`define B 16
`define C 17
`define D 18
`define E 19
`define F 20
`define G 21
`define H 22
`define I 23
`define J 24
`define K 25
`define L 26
`define M 27
`define N 28
`define O 29
`define P 30
`define Q 31
`define R 32
`define S 33
`define T 34
`define U 35
`define V 36
`define W 37
`define X 38
`define Y 39
`define Z 40
//=======================================================
//  This code is generated by Terasic System Builder
//=======================================================

module SDRAM_VGA(

    //////////// CLOCK //////////
    input                       ADC_CLK_10,
    input                       MAX10_CLK1_50,
    input                       MAX10_CLK2_50,

    //////////// SDRAM //////////
    output          [12:0]      DRAM_ADDR,
    output           [1:0]      DRAM_BA,
    output                      DRAM_CAS_N,
    output                      DRAM_CKE,
    output                      DRAM_CLK,
    output                      DRAM_CS_N,
    inout           [15:0]      DRAM_DQ,
    output                      DRAM_LDQM,
    output                      DRAM_RAS_N,
    output                      DRAM_UDQM,
    output                      DRAM_WE_N,

    //////////// SEG7 //////////
    output           [7:0]      HEX0,
    output           [7:0]      HEX1,
    output           [7:0]      HEX2,
    output           [7:0]      HEX3,
    output           [7:0]      HEX4,
    output           [7:0]      HEX5,

    //////////// KEY //////////
    input            [1:0]      KEY,

    //////////// LED //////////
    output           [9:0]      LEDR,

    //////////// SW //////////
    input            [9:0]      SW,

    //////////// VGA //////////
    output           [3:0]      VGA_B,
    output           [3:0]      VGA_G,
    output                      VGA_HS,
    output           [3:0]      VGA_R,
    output                      VGA_VS,

    //////////// Accelerometer //////////
    output                      GSENSOR_CS_N,
    input            [2:1]      GSENSOR_INT,
    output                      GSENSOR_SCLK,
    inout                       GSENSOR_SDI,
    inout                       GSENSOR_SDO,

    //////////// Arduino //////////
    inout           [15:0]      ARDUINO_IO,
    inout                       ARDUINO_RESET_N,

    //////////// GPIO, GPIO connect to GPIO Default //////////
    inout           [35:0]      GPIO
);


//=======================================================
//  REG/WIRE declarations
//=======================================================
wire VGA_CTRL_CLK, VGA_SYNC_CLK;
wire holdClk, ramClk;

//PLLRAM ramPll(MAX10_CLK2_50, holdClk, ramClk); //c1 sfasato di 3ns in ritardo. c0 usato per l'hold
PLLVGA pll1(MAX10_CLK1_50, VGA_CTRL_CLK, VGA_SYNC_CLK);

pll2 test(
    .inclk0(MAX10_CLK2_50),
    .c0(holdClk),
    .c1(ramClk));


integer count;
integer currentLine;
integer currentColumn;
integer x;
integer y;

reg [5:0] carattere;
integer size; //dimensione testo

reg [7:0]R_val;
reg [7:0]G_val;
reg [7:0]B_val;

//servono 25.175MHz (60Hz)
parameter Htime = 96;//41;      //clock
parameter Vtime = 2;//10;       //lines

parameter VBporch = 33;//2; //lines
parameter VFporch = 10;//2; //lines

parameter HBporch = 48;//2; //clk
parameter HFporch = 16;//2; //clk

parameter columns = 640;
parameter lines = 480;

parameter lineTime = (columns+HFporch+Htime+HBporch);   //th
parameter totalFrame = lineTime*(lines+VFporch+Vtime+VBporch);

assign VGA_HS = ((currentColumn) > (columns+HFporch) && (currentColumn < (columns+HFporch+Htime)));//HSYNC_val;
assign VGA_VS = ((currentLine) > (lines+VFporch) && (currentLine) < (lines+VFporch+Vtime));//VSYNC_val;

assign VGA_R[3:0] = R_val[3:0];
assign VGA_G[3:0] = G_val[3:0];
assign VGA_B[3:0] = B_val[3:0];

//tabella font
//n righe, n elementi, n colonne
reg [7:0] font [41][6] = '{
    '{8'h00,8'h00,8'h00,8'h00,8'h00,8'h00}, //   //0
    '{8'h30,8'h30,8'h00,8'h00,8'h00,8'h00}, // . //1
    '{8'h08,8'h08,8'h08,8'h08,8'h08,8'h00}, // - //2
    '{8'h40,8'h40,8'h40,8'h40,8'h40,8'h40}, // _    //3
    '{8'h24,8'h00,8'h00,8'h00,8'h00,8'h00}, // : //4
    '{8'h1e,8'h31,8'h29,8'h25,8'h23,8'h1e}, // 0 //5
    '{8'h22,8'h21,8'h3f,8'h20,8'h20,8'h20}, // 1 //6
    '{8'h32,8'h29,8'h29,8'h29,8'h29,8'h26}, // 2 //7
    '{8'h12,8'h21,8'h21,8'h25,8'h25,8'h1a}, // 3 //8
    '{8'h18,8'h14,8'h12,8'h3f,8'h10,8'h10}, // 4 //9
    '{8'h17,8'h25,8'h25,8'h25,8'h25,8'h19}, // 5 //10
    '{8'h1e,8'h25,8'h25,8'h25,8'h25,8'h18}, // 6 //11
    '{8'h01,8'h01,8'h31,8'h09,8'h05,8'h03}, // 7 //12
    '{8'h1a,8'h25,8'h25,8'h25,8'h25,8'h1a}, // 8 //13
    '{8'h06,8'h29,8'h29,8'h29,8'h29,8'h1e}, // 9 //14
    '{8'h3e,8'h09,8'h09,8'h09,8'h09,8'h3e}, // A //15
    '{8'h3f,8'h25,8'h25,8'h25,8'h25,8'h1a}, // B //16
    '{8'h1e,8'h21,8'h21,8'h21,8'h21,8'h12}, // C //17
    '{8'h3f,8'h21,8'h21,8'h21,8'h12,8'h0c}, // D //18
    '{8'h3f,8'h25,8'h25,8'h25,8'h25,8'h21}, // E //19
    '{8'h3f,8'h05,8'h05,8'h05,8'h05,8'h01}, // F //20
    '{8'h1e,8'h21,8'h21,8'h21,8'h29,8'h1a}, // G //21
    '{8'h3f,8'h04,8'h04,8'h04,8'h04,8'h3f}, // H //22
    '{8'h21,8'h21,8'h3f,8'h21,8'h21,8'h21}, // I //23
    '{8'h10,8'h20,8'h20,8'h20,8'h20,8'h1f}, // J //24
    '{8'h3f,8'h04,8'h0c,8'h0a,8'h11,8'h20}, // K //25
    '{8'h3f,8'h20,8'h20,8'h20,8'h20,8'h20}, // L //26
    '{8'h3f,8'h02,8'h04,8'h04,8'h02,8'h3f}, // M //27
    '{8'h3f,8'h02,8'h04,8'h08,8'h10,8'h3f}, // N //28
    '{8'h1e,8'h21,8'h21,8'h21,8'h21,8'h1e}, // O //29
    '{8'h3f,8'h09,8'h09,8'h09,8'h09,8'h06}, // P //30
    '{8'h1e,8'h21,8'h29,8'h31,8'h21,8'h1e}, // Q //31
    '{8'h3f,8'h09,8'h09,8'h09,8'h19,8'h26}, // R //32
    '{8'h12,8'h25,8'h25,8'h25,8'h25,8'h18}, // S //33
    '{8'h01,8'h01,8'h01,8'h3f,8'h01,8'h01}, // T //34
    '{8'h1f,8'h20,8'h20,8'h20,8'h20,8'h1f}, // U //35
    '{8'h0f,8'h10,8'h20,8'h20,8'h10,8'h0f}, // V //36
    '{8'h1f,8'h20,8'h10,8'h10,8'h20,8'h1f}, // W //37
    '{8'h21,8'h12,8'h0c,8'h0c,8'h12,8'h21}, // X //38
    '{8'h01,8'h02,8'h0c,8'h38,8'h04,8'h02}, // Y //39
    '{8'h21,8'h31,8'h29,8'h25,8'h23,8'h21}  // Z //40
};

//array che contiene le scritte
reg [5:0] arrayChar [columns/6][lines/8]; //6 = larghezza font - 8 = altezza font (8 solo perchè è un byte, ne usiamo solo 6 di bit)

//=======================================================
//  Structural coding
//=======================================================
always @(negedge VGA_CTRL_CLK)
begin
    if (count < totalFrame)
        count = count + 1;
    else
        count = 0;
end



always @(negedge VGA_CTRL_CLK)
begin
    currentColumn = count%lineTime;
    currentLine = count/lineTime;

    if ((currentLine) < lines && (currentColumn) < columns)
    begin //------0
            //sotto è prima modifica
            carattere = arrayChar[currentColumn/(8*size)][currentLine/(8*size)];//[currentColumn/6][currentLine/8]; //contiene l'indice del carattere scelto nella tabella dei caratteri "char" --- gli indici indicano la posizione sullo schermo
            //------ questo sotto funziona tutto
            if (font[carattere][(currentColumn/size)%8][(currentLine/size)%8]) //carattere, colonna e riga alla fine
            begin
                R_val [7:0] = 255;
                G_val [7:0] = 255;
                B_val [7:0] = 255;
            end
            else
            begin //------
                R_val [7:0] = 0;
                G_val [7:0] = 0;
                B_val [7:0] = 10;
            end //------
            //------
    end //------0
    else
    begin
    R_val [7:0] = 0;
    G_val [7:0] = 0;
    B_val [7:0] = 0;
    end


//-------
end //always


//scritta test memoria ram
always @(1)
begin
    size = 2;
    arrayChar[1][1] = `T;
    arrayChar[2][1] = `E;
    arrayChar[3][1] = `S;
    arrayChar[4][1] = `T;
    arrayChar[5][1] = `SPACE;
    arrayChar[6][1] = `M;
    arrayChar[7][1] = `E;
    arrayChar[8][1] = `M;
    arrayChar[9][1] = `O;
    arrayChar[10][1] = `R;
    arrayChar[11][1] = `I;
    arrayChar[12][1] = `A;
    arrayChar[13][1] = `SPACE;
    arrayChar[14][1] = `R;
    arrayChar[15][1] = `A;
    arrayChar[16][1] = `M;
    arrayChar[17][1] = `DOT;
    arrayChar[18][1] = `DOT;
    arrayChar[19][1] = `DOT;


end

wire readEmpty, readAvailable, writeFull, busy;
reg [15:0] OUTData [8];
reg [15:0] INData [8];

reg [1:0] rdBank = 2'b0;
wire [12:0] rdRow = {8'b0, SW[3:0]};
wire [9:0] rdColumn = {5'b0, SW[3:0]};

reg [1:0] wrBank = 2'b0;
wire [12:0] wrRow = {8'b0, SW[3:0]};
wire [9:0] wrColumn = {5'b0, SW[3:0]};

wire [7:0] currentCommand = {DRAM_CKE, DRAM_CS_N, DRAM_RAS_N, DRAM_CAS_N, DRAM_WE_N, DRAM_BA[1:0], DRAM_ADDR[10]};
always @(1)
begin
        INData[0][15:0] = {SW[9:4], SW[9:4], SW[9:4], SW[9:4]};

        arrayChar[1][4] = `A;
        arrayChar[2][4] = `D;
        arrayChar[3][4] = `D;
        arrayChar[4][4] = `R;
        arrayChar[5][4] = `COLON;
        arrayChar[6][4] =  SW[3:0]+5;

        arrayChar[1][5] = `I;
        arrayChar[2][5] = `N;
        arrayChar[3][5] = `P;
        arrayChar[4][5] = `T;
        arrayChar[5][5] = `COLON;
        arrayChar[6][5] =  INData[0][3:0]+5;

        arrayChar[1][6] = `O;
        arrayChar[2][6] = `U;
        arrayChar[3][6] = `P;
        arrayChar[4][6] = `T;
        arrayChar[5][6] = `COLON;

        arrayChar[6][7] =  OUTData[0][3:0]+5;
        arrayChar[7][7] =  OUTData[0][7:4]+5;
        arrayChar[8][7] =  OUTData[0][11:8]+5;
        arrayChar[9][7] =  OUTData[0][15:12]+5;

        arrayChar[11][7] =  OUTData[1][3:0]+5;
        arrayChar[12][7] =  OUTData[1][7:4]+5;
        arrayChar[13][7] =  OUTData[1][11:8]+5;
        arrayChar[14][7] =  OUTData[1][15:12]+5;

        arrayChar[16][7] =  OUTData[2][3:0]+5;
        arrayChar[17][7] =  OUTData[2][7:4]+5;
        arrayChar[18][7] =  OUTData[2][11:8]+5;
        arrayChar[19][7] =  OUTData[2][15:12]+5;

        arrayChar[21][7] =  OUTData[3][3:0]+5;
        arrayChar[22][7] =  OUTData[3][7:4]+5;
        arrayChar[23][7] =  OUTData[3][11:8]+5;
        arrayChar[24][7] =  OUTData[3][15:12]+5;

        arrayChar[6][8] =  OUTData[4][3:0]+5;
        arrayChar[7][8] =  OUTData[4][7:4]+5;
        arrayChar[8][8] =  OUTData[4][11:8]+5;
        arrayChar[9][8] =  OUTData[4][15:12]+5;

        arrayChar[11][8] =  OUTData[5][3:0]+5;
        arrayChar[12][8] =  OUTData[5][7:4]+5;
        arrayChar[13][8] =  OUTData[5][11:8]+5;
        arrayChar[14][8] =  OUTData[5][15:12]+5;

        arrayChar[16][8] =  OUTData[6][3:0]+5;
        arrayChar[17][8] =  OUTData[6][7:4]+5;
        arrayChar[18][8] =  OUTData[6][11:8]+5;
        arrayChar[19][8] =  OUTData[6][15:12]+5;

        arrayChar[21][8] =  OUTData[7][3:0]+5;
        arrayChar[22][8] =  OUTData[7][7:4]+5;
        arrayChar[23][8] =  OUTData[7][11:8]+5;
        arrayChar[24][8] =  OUTData[7][15:12]+5;





end

reg reset_n, readRq, writeRq;
button breset_n(SW[9], MAX10_CLK1_50, 1, reset_n);
button breadRq(~KEY[0], MAX10_CLK1_50, 1, readRq);
button bwriteRq(~KEY[1], MAX10_CLK1_50, 1, writeRq);
assign LEDR[5] = 1;
assign LEDR[9] = SW[9];
assign LEDR[8] = holdClk;
assign LEDR[7] = ramClk;
SDRAM_CONTROLLER miaRam(
    SW[9],
    holdClk, //il PLL viene implementato qui (cioè dentro il file SDRAM_CONTROLLER.v) stesso (così come le FIFO)
    ramClk,
    /////////////////////////////

    //read FIFO (tutti gli altri pin delle FIFo vengono definiti successivamente quando verranno inizializzate le FIFO)

    readEmpty,      //controlla se la FIFO di lettura è vuota
    OUTData,        //da qui vengono prelevati i dati appena letti dalla RAM

    //fine read FIFO

    readAvailable,      //=1 se la lettura è stata eseguita e quindi dato disponibile in dataUT (??)
    readRq,                 //=1 quando si vuole eseguire una lettura (una volta completata la lettura)
    rdBank,             //seleziona il bank
    rdRow,              //seleziona la linea
    rdColumn,           //seleziona la colonna

    /////////////////////////////

    //write FIFO

    writeFull,      //controlla se la FIFO di scrittura è piena
    INData, //riceve i dati che verranno scritti in RAM

    //fine write FIFO

//  output writeBusy,               //durante una scrittura viene posto a 1 e impedisce scritture "contemporanee"
    writeRq,                    //=1 quando si vuole eseguire una scrittura
    wrBank,             //seleziona il bank di partenza
    wrRow,              //seleziona la linea di partenza
    wrColumn,           //seleziona la colonna di partenza

    LEDR[1],

    //////////// SDRAM //////////
DRAM_ADDR[12:0],
DRAM_BA[1:0],
DRAM_CAS_N,
DRAM_CKE,
DRAM_CLK,
DRAM_CS_N,
DRAM_DQ[15:0],
DRAM_LDQM,
DRAM_RAS_N,
DRAM_UDQM,
DRAM_WE_N,
LEDR[0]
);


//wire mioClk;
//clk_div asd(MAX10_CLK1_50, 1, 50, mioClk);
//
//always @(posedge mioClk)
//begin
//  readRq = ~KEY[0];
//  writeRq = ~KEY[1];
//end

//reg [12:0] DRAM_ADDR_reg;
//reg [1:0] DRAM_BA_reg;
//reg DRAM_CAS_N_reg;
//reg DRAM_CKE_reg;
//reg DRAM_CLK_reg;
//reg DRAM_CS_N_reg;
//reg [15:0] DRAM_DQ_reg;
//reg DRAM_LDQM_reg;
//reg DRAM_RAS_N_reg;
//reg DRAM_UDQM_reg;
//reg DRAM_WE_N_reg;


//  assign DRAM_ADDR = DRAM_ADDR_reg;
//  assign DRAM_BA = DRAM_BA_reg;
//  assign DRAM_CAS_N = DRAM_CAS_N_reg;
//  assign DRAM_CKE = DRAM_CKE_reg;
//  assign DRAM_CLK = DRAM_CLK_reg;
//  assign DRAM_CS_N = DRAM_CS_N_reg;
//  assign DRAM_DQ = DRAM_DQ_reg;
//  assign DRAM_LDQM = DRAM_LDQM_reg;
//  assign DRAM_RAS_N = DRAM_RAS_N_reg;
//  assign DRAM_UDQM = DRAM_UDQM_reg;
//  assign DRAM_WE_N = DRAM_WE_N_reg;

endmodule

//--------- MODULO CHE CI PERMETTE DI DIVIDERE IL CLOCK IN UNA FREQUENZA QUALSIASI
module clk_div(input clk_in, input [31:0] freq, input [7:0] duty_cycle, output reg clk_out);
integer count;
always @ (posedge clk_in)
  begin
    if (count==((2000/freq)-1))
       count <= 0;
    else count <= count+1;
        clk_out  <=  (count > (2000/freq)/(100/(100-duty_cycle)));
  end
endmodule
//------------------------------------------------------------------------------------------

//-------- MODULO FLIP FLOP EDGE-TRIGGERED D ---
module FFD(input D, input clk, input rst_n, output Q);
    reg q;
    assign Q = q;

    always @(posedge clk)
     if (~rst_n)
        begin
            q <= 1'b0;
        end
     else
        begin
            q <= D;
        end

endmodule
//---------------------------------------------

//--------- MODULO CHE RENDE UN INPUT "MONOSTABILE" ------------------
module button(input x, input clk, input rst_n, output out);
wire M;
wire N;

wire Dm;
wire Dn = x;
wire y;

and(Dm, N, x);
xor(y, M, N);

FFD m(Dm, clk, rst_n, M);
FFD n(Dn, clk, rst_n, N);

assign out = y;

endmodule
//------------------------------------------------------------------------