module test #(
    parameter integer WIDTH = 32
)(
    input clk, rst,
    input start,
    input [7:0] data_in,
    output reg [WIDTH - 1:0] data
);

    localparam integer N = WIDTH / 8;

    reg [N-1:0] ena;

    always @(posedge clk)
        if (rst)
            ena <= 0;
        else
            ena <= { ena[N-2:0], start };

    integer i;
    always @(posedge clk)
        for (i=0; i<N; i=i+1)
            if (ena[i])
                data[8*i+:8] <= data_in;

endmodule