module STATE_MACHINE (
    input CLK, E, RESET,
    output [1:0] Z
);

    reg [1:0] ACTUAL_STATE;
    reg [1:0] NEXT_STATE;
    reg [1:0] Z_INT;

    parameter Z1=2'b00, Z2=2'b01, Z3=2'b10, Z4=2'b11;





  always @(posedge CLK)
begin : STATE_MEM
    if (RESET == 1) begin

        ACTUAL_STATE <= Z1;
    end else begin
        ACTUAL_STATE <= NEXT_STATE;
    end
end


always @(ACTUAL_STATE, E)
begin : OUTPUT_LOGIC
   case (ACTUAL_STATE)
   Z1 : begin
      Z_INT<=Z1;
      end
   Z2 : begin
      Z_INT<=2'b01;
      end
   Z3 : begin
      Z_INT<=2'b10;
      end
   Z4 : begin
      Z_INT<=2'b11;
      end
endcase


end

assign Z=Z_INT;
always @(ACTUAL_STATE, E)
begin : OUTPUT_LOGICee
case (ACTUAL_STATE)
   Z1 : begin
    case (E)
       1 : NEXT_STATE<= Z2;
       0 : NEXT_STATE<= Z2;
    endcase
   end

   Z2 : begin
    case (E)
       1 : NEXT_STATE<= Z3;
       0 : NEXT_STATE<= Z4;
    endcase
   end

   Z3 : begin
    case (E)
       1 : NEXT_STATE<= Z4;
       0 : NEXT_STATE<= Z1;
    endcase
   end

   Z4 : begin
    case (E)
       1 : NEXT_STATE<= Z1;
       0 : NEXT_STATE<= Z3;
    endcase
   end

endcase
end