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  1. `timescale 1ns / 1ps
  2.  
  3.  
  4. module tb_or_gate
  5. (
  6. );
  7.  reg[9:0] r_data_test_in=0;
  8.  wire data_test_out;
  9.  wire [9:0] data_test_in;
  10.  reg clk=1'b0;
  11.  initial
  12.  begin
  13.     while(1)
  14.     begin
  15.         #1; clk=1'b1;
  16.         #1; clk=1'b0;
  17.     end
  18.  end
  19.  
  20.  always @(posedge clk)
  21.  begin
  22.     r_data_test_in<=r_data_test_in+1;
  23.  end
  24.     assign data_test_in=r_data_test_in;
  25.  
  26.     or_gate testbench
  27.     (
  28.         .i(data_test_in),
  29.         .o(data_test_out)
  30.     );
  31.    
  32.    
  33.    
  34.    verify test
  35.    (
  36.     .data_test_in1(data_test_in),
  37.     .data_test_out1(data_test_out),
  38.     .clk(clk)
  39.    );
  40. endmodule
  41.  
  42.  
  43. module verify
  44. (
  45.     input [9:0] data_test_in1,
  46.     input data_test_out1,
  47.     input clk
  48. );
  49. integer file;
  50. reg[3:0]i;
  51.     always @(negedge clk)
  52.     begin
  53.    
  54.         if(((data_test_in1 !={10{1'b0}})&&(data_test_out1==1'b0))||((data_test_in1 =={10{1'b0}})&&(data_test_out1==1'b1)))
  55.         begin
  56.            file=$fopen("C:/Users/Konrad/Desktop/Systemy_Rekonfigurowalne/Lab2/domowe_v3/log5.txt","a");
  57.             $fwrite(file,"Dane:\n");
  58.             for(i=0;i<10;i=i+1)
  59.             begin
  60.                
  61.                 $fwrite(file,"%b",data_test_in1[i]);
  62.             end
  63.             $fwrite(file,"\n Otrzymany wynik: %b \n",data_test_out1);
  64.             $fclose(file);
  65.             end
  66.    
  67.    end
  68. endmodule
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