`timescale 1ns / 1ps


module tb_or_gate
(
);
 reg[9:0] r_data_test_in=0;
 wire data_test_out;
 wire [9:0] data_test_in;
 reg clk=1'b0;
 initial
 begin
    while(1)
    begin
        #1; clk=1'b1;
        #1; clk=1'b0;
    end
 end

 always @(posedge clk)
 begin
    r_data_test_in<=r_data_test_in+1;
 end
    assign data_test_in=r_data_test_in;

    or_gate testbench
    (
        .i(data_test_in),
        .o(data_test_out)
    );



   verify test
   (
    .data_test_in1(data_test_in),
    .data_test_out1(data_test_out),
    .clk(clk)
   );
endmodule


module verify
(
    input [9:0] data_test_in1,
    input data_test_out1,
    input clk
);
integer file;
reg[3:0]i;
    always @(negedge clk)
    begin

        if(((data_test_in1 !={10{1'b0}})&&(data_test_out1==1'b0))||((data_test_in1 =={10{1'b0}})&&(data_test_out1==1'b1)))
        begin
           file=$fopen("C:/Users/Konrad/Desktop/Systemy_Rekonfigurowalne/Lab2/domowe_v3/log5.txt","a");
            $fwrite(file,"Dane:\n");
            for(i=0;i<10;i=i+1)
            begin

                $fwrite(file,"%b",data_test_in1[i]);
            end
            $fwrite(file,"\n Otrzymany wynik: %b \n",data_test_out1);
            $fclose(file);
            end

   end
endmodule