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  1. /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
  2. /*
  3. * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
  4. * Author: STM32CubeMX code generation for STMicroelectronics.
  5. */
  6.  
  7. /* For more information on Device Tree configuration, please refer to
  8. * https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
  9. */
  10.  
  11. /dts-v1/;
  12. #include <dt-bindings/pinctrl/stm32-pinfunc.h>
  13. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  14. #include <dt-bindings/soc/st,stm32-etzpc.h>
  15. #include "stm32mp15-mx.dtsi"
  16.  
  17. #include "stm32mp153.dtsi"
  18. #include "stm32mp15xa.dtsi"
  19. #include "stm32mp15xxac-pinctrl.dtsi"
  20. #include "stm32mp15-ddr.dtsi"
  21.  
  22. /* USER CODE BEGIN includes */
  23. #include <dt-bindings/power/stm32mp1-power.h>
  24. /* USER CODE END includes */
  25.  
  26. / {
  27. model = "STMicroelectronics custom STM32CubeMX board - openstlinux-5.10-dunfell-mp1-21-11-17";
  28. compatible = "st,stm32mp153a-custom_board-mx", "st,stm32mp153";
  29.  
  30. memory@c0000000 {
  31. device_type = "memory";
  32. reg = <0xc0000000 0x20000000>;
  33.  
  34. /* USER CODE BEGIN memory */
  35. /* USER CODE END memory */
  36. };
  37.  
  38. /* USER CODE BEGIN root */
  39.  
  40. vin:vin{
  41. compatible = "regulator-fixed";
  42. regulator-name = "vin";
  43. regulator-min-microvolt = <5000000>;
  44. regulator-max-microvolt = <5000000>;
  45. regulator-always-on;
  46. };
  47.  
  48. aliases{
  49. serial0 = &uart4;
  50. serial1 = &usart3;
  51. serial2 = &uart7;
  52. };
  53.  
  54. chosen{
  55. stdout-path = "serial0:115200n8";
  56. };
  57. /* USER CODE END root */
  58.  
  59. clocks {
  60. /* USER CODE BEGIN clocks */
  61. /* USER CODE END clocks */
  62.  
  63. clk_lse: clk-lse {
  64. st,drive = < LSEDRV_MEDIUM_HIGH >;
  65.  
  66. /* USER CODE BEGIN clk_lse */
  67. /* USER CODE END clk_lse */
  68. };
  69.  
  70. clk_hse: clk-hse {
  71. st,digbypass;
  72.  
  73. /* USER CODE BEGIN clk_hse */
  74. /* USER CODE END clk_hse */
  75. };
  76. };
  77.  
  78. }; /*root*/
  79.  
  80. &pinctrl {
  81. sdmmc1_pins_mx: sdmmc1_mx-0 {
  82. pins1 {
  83. pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
  84. <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
  85. <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
  86. <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
  87. <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
  88. bias-disable;
  89. drive-push-pull;
  90. slew-rate = <1>;
  91. };
  92. pins2 {
  93. pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
  94. bias-disable;
  95. drive-push-pull;
  96. slew-rate = <3>;
  97. };
  98. };
  99.  
  100. uart4_pins_mx: uart4_mx-0 {
  101. pins1 {
  102. pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
  103. bias-disable;
  104. };
  105. pins2 {
  106. pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
  107. bias-disable;
  108. drive-push-pull;
  109. slew-rate = <0>;
  110. };
  111. };
  112.  
  113. uart7_pins_mx: uart7_mx-0 {
  114. pins1 {
  115. pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
  116. bias-disable;
  117. };
  118. pins2 {
  119. pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
  120. bias-disable;
  121. drive-push-pull;
  122. slew-rate = <0>;
  123. };
  124. };
  125.  
  126. /* USER CODE BEGIN pinctrl */
  127. /* USER CODE END pinctrl */
  128. };
  129.  
  130. &pinctrl_z {
  131. i2c4_pins_z_mx: i2c4_mx-0 {
  132. pins {
  133. pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
  134. <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
  135. bias-disable;
  136. drive-open-drain;
  137. slew-rate = <0>;
  138. };
  139. };
  140.  
  141. /* USER CODE BEGIN pinctrl_z */
  142. /* USER CODE END pinctrl_z */
  143. };
  144.  
  145. &bsec{
  146. status = "okay";
  147. secure-status = "okay";
  148.  
  149. /* USER CODE BEGIN bsec */
  150.  
  151. board_id:board_id@ec{
  152. reg = <0xec 0x4>;
  153. st,non-secure-otp;
  154. };
  155. /* USER CODE END bsec */
  156. };
  157.  
  158. &etzpc{
  159. secure-status = "okay";
  160. st,decprot = <
  161. /*"NS_R S_W" peripherals*/
  162. DECPROT(STM32MP1_ETZPC_DDRCTRL_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)
  163. DECPROT(STM32MP1_ETZPC_DDRPHYC_ID, DECPROT_NS_R_S_W, DECPROT_LOCK)
  164. /*"Non Secured" peripherals*/
  165. DECPROT(STM32MP1_ETZPC_DMA1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  166. DECPROT(STM32MP1_ETZPC_DMAMUX_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  167. DECPROT(STM32MP1_ETZPC_ETH_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  168. DECPROT(STM32MP1_ETZPC_HASH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  169. DECPROT(STM32MP1_ETZPC_I2C1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  170. DECPROT(STM32MP1_ETZPC_I2C2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  171. DECPROT(STM32MP1_ETZPC_I2C3_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  172. DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  173. DECPROT(STM32MP1_ETZPC_I2C5_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  174. DECPROT(STM32MP1_ETZPC_RNG1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  175. DECPROT(STM32MP1_ETZPC_SPI2_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  176. DECPROT(STM32MP1_ETZPC_SPI3_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  177. DECPROT(STM32MP1_ETZPC_SPI6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  178. DECPROT(STM32MP1_ETZPC_TIM1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  179. DECPROT(STM32MP1_ETZPC_TIM6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  180. DECPROT(STM32MP1_ETZPC_TIM8_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  181. DECPROT(STM32MP1_ETZPC_UART4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  182. DECPROT(STM32MP1_ETZPC_UART7_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  183. DECPROT(STM32MP1_ETZPC_OTG_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  184. DECPROT(STM32MP1_ETZPC_VREFBUF_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
  185. /*"Secured" peripherals*/
  186. DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_UNLOCK)
  187. /*"Mcu Isolation" peripherals*/
  188. DECPROT(STM32MP1_ETZPC_DMA2_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
  189. DECPROT(STM32MP1_ETZPC_SPI1_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
  190. DECPROT(STM32MP1_ETZPC_SPI4_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
  191. DECPROT(STM32MP1_ETZPC_SPI5_ID, DECPROT_MCU_ISOLATION, DECPROT_UNLOCK)
  192.  
  193. /*Restriction: following IDs are not managed - please to use User-Section if needed:
  194. STM32MP1_ETZPC_SRAMx_ID STM32MP1_ETZPC_RETRAM_ID STM32MP1_ETZPC_BKPSRAM_ID*/
  195.  
  196. /* USER CODE BEGIN etzpc_decprot */
  197. /*STM32CubeMX generates a basic and standard configuration for ETZPC.
  198. Additional device configurations can be added here if needed.
  199. "etzpc" node could be also overloaded in "addons" User-Section.*/
  200.  
  201. DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_UNLOCK)
  202.  
  203. /* USER CODE END etzpc_decprot */
  204. >;
  205.  
  206. /* USER CODE BEGIN etzpc */
  207. /* USER CODE END etzpc */
  208. };
  209.  
  210. &hash1{
  211. status = "okay";
  212.  
  213. /* USER CODE BEGIN hash1 */
  214. /* USER CODE END hash1 */
  215. };
  216.  
  217. &i2c4{
  218. pinctrl-names = "default";
  219. pinctrl-0 = <&i2c4_pins_z_mx>;
  220. status = "okay";
  221. secure-status = "okay";
  222.  
  223. /* USER CODE BEGIN i2c4 */
  224. i2c-scl-rising-time-ns = <185>;
  225. i2c-scl-falling-time-ns = <20>;
  226. clock-frequency = <400000>;
  227.  
  228. pmic:stpmic@33{
  229. compatible = "st,stpmic1";
  230. reg = <0x33>;
  231. interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
  232. interrupt-controller;
  233. #interrupt-cells = <2>;
  234. status = "okay";
  235. secure-status = "okay";
  236.  
  237. regulators{
  238. compatible = "st,stpmic1-regulators";
  239. buck1-supply = <&vin>;
  240. buck2-supply = <&vin>;
  241. buck3-supply = <&vin>;
  242. buck4-supply = <&vin>;
  243. ldo1-supply = <&v3v3>;
  244. ldo2-supply = <&vin>;
  245. ldo3-supply = <&vdd_ddr>;
  246. ldo4-supply = <&vin>;
  247. ldo5-supply = <&vin>;
  248. ldo6-supply = <&v3v3>;
  249. vref_ddr-supply = <&vin>;
  250. boost-supply = <&vin>;
  251. pwr_sw1-supply = <&bst_out>;
  252. pwr_sw2-supply = <&bst_out>;
  253.  
  254. vddcore:buck1{
  255. regulator-name = "vddcore";
  256. regulator-min-microvolt = <1200000>;
  257. regulator-max-microvolt = <1350000>;
  258. regulator-always-on;
  259. regulator-initial-mode = <0>;
  260. regulator-over-current-protection;
  261.  
  262. lp-stop{
  263. regulator-on-in-suspend;
  264. regulator-suspend-microvolt = <1200000>;
  265. };
  266.  
  267. standby-ddr-sr{
  268. regulator-off-in-suspend;
  269. };
  270.  
  271. standby-ddr-off{
  272. regulator-off-in-suspend;
  273. };
  274. };
  275.  
  276. vdd_ddr:buck2{
  277. regulator-name = "vdd_ddr";
  278. regulator-min-microvolt = <1350000>;
  279. regulator-max-microvolt = <1350000>;
  280. regulator-always-on;
  281. regulator-initial-mode = <0>;
  282. regulator-over-current-protection;
  283.  
  284. lp-stop{
  285. regulator-suspend-microvolt = <1350000>;
  286. regulator-on-in-suspend;
  287. };
  288.  
  289. standby-ddr-sr{
  290. regulator-suspend-microvolt = <1350000>;
  291. regulator-on-in-suspend;
  292. };
  293.  
  294. standby-ddr-off{
  295. regulator-off-in-suspend;
  296. };
  297. };
  298.  
  299. vdd:buck3{
  300. regulator-name = "vdd";
  301. regulator-min-microvolt = <3300000>;
  302. regulator-max-microvolt = <3300000>;
  303. regulator-always-on;
  304. st,mask-reset;
  305. regulator-initial-mode = <0>;
  306. regulator-over-current-protection;
  307.  
  308. lp-stop{
  309. regulator-suspend-microvolt = <3300000>;
  310. regulator-on-in-suspend;
  311. };
  312.  
  313. standby-ddr-sr{
  314. regulator-suspend-microvolt = <3300000>;
  315. regulator-on-in-suspend;
  316. };
  317.  
  318. standby-ddr-off{
  319. regulator-suspend-microvolt = <3300000>;
  320. regulator-on-in-suspend;
  321. };
  322. };
  323.  
  324. v3v3:buck4{
  325. regulator-name = "v3v3";
  326. regulator-min-microvolt = <3300000>;
  327. regulator-max-microvolt = <3300000>;
  328. regulator-always-on;
  329. regulator-over-current-protection;
  330. regulator-initial-mode = <0>;
  331.  
  332. lp-stop{
  333. regulator-suspend-microvolt = <3300000>;
  334. regulator-on-in-suspend;
  335. };
  336.  
  337. standby-ddr-sr{
  338. regulator-off-in-suspend;
  339. };
  340.  
  341. standby-ddr-off{
  342. regulator-off-in-suspend;
  343. };
  344. };
  345.  
  346. v1v8_audio:ldo1{
  347. regulator-name = "v1v8_audio";
  348. regulator-min-microvolt = <1800000>;
  349. regulator-max-microvolt = <1800000>;
  350. regulator-always-on;
  351.  
  352. standby-ddr-sr{
  353. regulator-off-in-suspend;
  354. };
  355.  
  356. standby-ddr-off{
  357. regulator-off-in-suspend;
  358. };
  359. };
  360.  
  361. v3v3_hdmi:ldo2{
  362. regulator-name = "v3v3_hdmi";
  363. regulator-min-microvolt = <3300000>;
  364. regulator-max-microvolt = <3300000>;
  365. regulator-always-on;
  366.  
  367. standby-ddr-sr{
  368. regulator-off-in-suspend;
  369. };
  370.  
  371. standby-ddr-off{
  372. regulator-off-in-suspend;
  373. };
  374. };
  375.  
  376. vtt_ddr:ldo3{
  377. regulator-name = "vtt_ddr";
  378. regulator-always-on;
  379. regulator-over-current-protection;
  380. st,regulator-sink-source;
  381.  
  382. lp-stop{
  383. regulator-off-in-suspend;
  384. };
  385.  
  386. standby-ddr-sr{
  387. regulator-off-in-suspend;
  388. };
  389.  
  390. standby-ddr-off{
  391. regulator-off-in-suspend;
  392. };
  393. };
  394.  
  395. vdd_usb:ldo4{
  396. regulator-name = "vdd_usb";
  397. regulator-min-microvolt = <3300000>;
  398. regulator-max-microvolt = <3300000>;
  399.  
  400. standby-ddr-sr{
  401. regulator-off-in-suspend;
  402. };
  403.  
  404. standby-ddr-off{
  405. regulator-off-in-suspend;
  406. };
  407. };
  408.  
  409. vdda:ldo5{
  410. regulator-name = "vdda";
  411. regulator-min-microvolt = <2900000>;
  412. regulator-max-microvolt = <2900000>;
  413. regulator-boot-on;
  414.  
  415. standby-ddr-sr{
  416. regulator-off-in-suspend;
  417. };
  418.  
  419. standby-ddr-off{
  420. regulator-off-in-suspend;
  421. };
  422. };
  423.  
  424. v1v2_hdmi:ldo6{
  425. regulator-name = "v1v2_hdmi";
  426. regulator-min-microvolt = <1200000>;
  427. regulator-max-microvolt = <1200000>;
  428. regulator-always-on;
  429.  
  430. standby-ddr-sr{
  431. regulator-off-in-suspend;
  432. };
  433.  
  434. standby-ddr-off{
  435. regulator-off-in-suspend;
  436. };
  437. };
  438.  
  439. vref_ddr:vref_ddr{
  440. regulator-name = "vref_ddr";
  441. regulator-always-on;
  442.  
  443. lp-stop{
  444. regulator-on-in-suspend;
  445. };
  446.  
  447. standby-ddr-sr{
  448. regulator-on-in-suspend;
  449. };
  450.  
  451. standby-ddr-off{
  452. regulator-off-in-suspend;
  453. };
  454. };
  455.  
  456. bst_out:boost{
  457. regulator-name = "bst_out";
  458. };
  459.  
  460. vbus_otg:pwr_sw1{
  461. regulator-name = "vbus_otg";
  462. };
  463.  
  464. vbus_sw:pwr_sw2{
  465. regulator-name = "vbus_sw";
  466. regulator-active-discharge = <1>;
  467. };
  468. };
  469. };
  470. /* USER CODE END i2c4 */
  471. };
  472.  
  473. &iwdg2{
  474. status = "okay";
  475. secure-status = "okay";
  476.  
  477. /* USER CODE BEGIN iwdg2 */
  478. timeout-sec = <32>;
  479. secure-timeout-sec = <5>;
  480. /* USER CODE END iwdg2 */
  481. };
  482.  
  483. &pwr_regulators{
  484. status = "okay";
  485. secure-status = "okay";
  486.  
  487. /* USER CODE BEGIN pwr_regulators */
  488. system_suspend_supported_soc_modes = <
  489. STM32_PM_CSLEEP_RUN
  490. STM32_PM_CSTOP_ALLOW_LP_STOP
  491. STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR
  492. >;
  493. system_off_soc_mode = <STM32_PM_CSTOP_ALLOW_STANDBY_DDR_OFF>;
  494. vdd-supply = <&vdd>;
  495. vdd_3v3_usbfs-supply = <&vdd_usb>;
  496. /* USER CODE END pwr_regulators */
  497. };
  498.  
  499. &rcc{
  500. status = "okay";
  501. secure-status = "okay";
  502. st,csi-cal;
  503. st,hsi-cal;
  504. st,cal-sec = <60>;
  505. st,clksrc = <
  506. CLK_MPU_PLL1P
  507. CLK_AXI_PLL2P
  508. CLK_MCU_PLL3P
  509. CLK_PLL12_HSE
  510. CLK_PLL3_HSE
  511. CLK_PLL4_HSE
  512. CLK_RTC_LSE
  513. CLK_MCO1_DISABLED
  514. CLK_MCO2_DISABLED
  515. >;
  516. st,clkdiv = <
  517. 1 /*MPU*/
  518. 0 /*AXI*/
  519. 0 /*MCU*/
  520. 1 /*APB1*/
  521. 1 /*APB2*/
  522. 1 /*APB3*/
  523. 1 /*APB4*/
  524. 2 /*APB5*/
  525. 0 /*RTC*/
  526. 0 /*MCO1*/
  527. 0 /*MCO2*/
  528. >;
  529. st,pkcs = <
  530. CLK_CKPER_DISABLED
  531. CLK_ETH_PLL4P
  532. CLK_SDMMC12_PLL4P
  533. CLK_STGEN_HSE
  534. CLK_USBPHY_HSE
  535. CLK_SPI2S1_PLL4P
  536. CLK_SPI2S23_PLL4P
  537. CLK_SPI45_PCLK2
  538. CLK_SPI6_HSI
  539. CLK_I2C46_HSI
  540. CLK_SDMMC3_DISABLED
  541. CLK_USBO_USBPHY
  542. CLK_ADC_DISABLED
  543. CLK_CEC_DISABLED
  544. CLK_I2C12_PCLK1
  545. CLK_I2C35_PCLK1
  546. CLK_UART1_DISABLED
  547. CLK_UART24_PCLK1
  548. CLK_UART35_DISABLED
  549. CLK_UART6_DISABLED
  550. CLK_UART78_PCLK1
  551. CLK_SPDIF_DISABLED
  552. CLK_SAI1_DISABLED
  553. CLK_SAI2_DISABLED
  554. CLK_SAI3_DISABLED
  555. CLK_SAI4_DISABLED
  556. CLK_RNG1_LSI
  557. CLK_LPTIM1_DISABLED
  558. CLK_LPTIM23_DISABLED
  559. CLK_LPTIM45_DISABLED
  560. >;
  561. pll1:st,pll@0 {
  562. compatible = "st,stm32mp1-pll";
  563. reg = <0>;
  564. cfg = < 2 80 0 1 1 PQR(1,0,0) >;
  565. frac = < 0x800 >;
  566. };
  567. pll2:st,pll@1 {
  568. compatible = "st,stm32mp1-pll";
  569. reg = <1>;
  570. cfg = < 2 65 1 1 0 PQR(1,0,1) >;
  571. frac = < 0x1400 >;
  572. };
  573. pll3:st,pll@2 {
  574. compatible = "st,stm32mp1-pll";
  575. reg = <2>;
  576. cfg = < 1 51 2 1 1 PQR(1,0,0) >;
  577. };
  578. pll4:st,pll@3 {
  579. compatible = "st,stm32mp1-pll";
  580. reg = <3>;
  581. cfg = < 3 98 5 5 1 PQR(1,0,0) >;
  582. };
  583.  
  584. /* USER CODE BEGIN rcc */
  585. /* USER CODE END rcc */
  586. };
  587.  
  588. &rng1{
  589. status = "okay";
  590. secure-status = "okay";
  591.  
  592. /* USER CODE BEGIN rng1 */
  593. /* USER CODE END rng1 */
  594. };
  595.  
  596. &rtc{
  597. status = "okay";
  598. secure-status = "okay";
  599.  
  600. /* USER CODE BEGIN rtc */
  601. /* USER CODE END rtc */
  602. };
  603.  
  604. &sdmmc1{
  605. pinctrl-names = "default";
  606. pinctrl-0 = <&sdmmc1_pins_mx>;
  607. status = "okay";
  608.  
  609. /* USER CODE BEGIN sdmmc1 */
  610. disable-wp;
  611. st,neg-edge;
  612. bus-width = <4>;
  613. vmmc-supply = <&v3v3>;
  614. /* USER CODE END sdmmc1 */
  615. };
  616.  
  617. &tamp{
  618. status = "okay";
  619. secure-status = "okay";
  620.  
  621. /* USER CODE BEGIN tamp */
  622. /* USER CODE END tamp */
  623. };
  624.  
  625. &uart4{
  626. pinctrl-names = "default";
  627. pinctrl-0 = <&uart4_pins_mx>;
  628. status = "okay";
  629.  
  630. /* USER CODE BEGIN uart4 */
  631. /* USER CODE END uart4 */
  632. };
  633.  
  634. &uart7{
  635. pinctrl-names = "default";
  636. pinctrl-0 = <&uart7_pins_mx>;
  637. status = "okay";
  638.  
  639. /* USER CODE BEGIN uart7 */
  640. /* USER CODE END uart7 */
  641. };
  642.  
  643. /* USER CODE BEGIN addons */
  644.  
  645. &cpu0{
  646. cpu-supply = <&vddcore>;
  647. };
  648.  
  649. &cpu1{
  650. cpu-supply = <&vddcore>;
  651. };
  652.  
  653. &nvmem_layout{
  654. nvmem-cells = <&cfg0_otp>,
  655. <&part_number_otp>,
  656. <&monotonic_otp>,
  657. <&nand_otp>,
  658. <&uid_otp>,
  659. <&package_otp>,
  660. <&hw2_otp>,
  661. <&pkh_otp>,
  662. <&board_id>;
  663. nvmem-cell-names = "cfg0_otp",
  664. "part_number_otp",
  665. "monotonic_otp",
  666. "nand_otp",
  667. "uid_otp",
  668. "package_otp",
  669. "hw2_otp",
  670. "pkh_otp",
  671. "board_id";
  672. };
  673.  
  674. &timers15{
  675. secure-status = "okay";
  676. st,hsi-cal-input = <7>;
  677. st,csi-cal-input = <8>;
  678. };
  679. /* USER CODE END addons */
  680.  
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