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  1. import serial
  2. import serial.tools.list_ports
  3. #Register Mapping
  4. cSUR1addr = 0
  5. cSUR2addr = 1
  6. cSUR3addr = 2
  7. cDACARaddr = 3
  8. cDACDRaddr = 4
  9. cX0Raddr = 5
  10. cX1Raddr = 6
  11. cX2Raddr = 7
  12. cX3Raddr = 8
  13. cSR1addr = 9
  14. cMISCCRaddr = 10
  15. cSR2addr = 11
  16. cREVRaddr = 14
  17.  
  18. commstr = [None]*10
  19.  
  20.  
  21. class USBcount50:
  22.  
  23.    
  24.     #Serialport instance
  25.     porthandles = []
  26.     global commstr
  27.     devcnt = 0
  28.    
  29.     def __init__(self):
  30.         ports = list(serial.tools.list_ports.comports())
  31.         for p in ports:
  32.             #USB_DEVICE(0x10C4, 0xF004),Elan Digital Systems USBcount50
  33.             if(p.vid == 0x10C4 and p.pid == 0xF004):
  34.             #if(p.vid == 0x10C4 and p.pid == 0xEA60):
  35.                 #print("Device found")
  36.                 self.porthandles.append(serial.Serial(p.device, baudrate=921600,timeout=0.05))
  37.        
  38.         self.devcnt = len(self.porthandles)
  39.         print("Device count : " + str(self.devcnt))
  40.  
  41. #from DLL v1.0.0.2 (USBcount50Drvr.cpp)
  42.     def Close(self, channel):
  43.         if(self.porthandles[channel] != None):
  44.             self.porthandles[channel].close()          
  45.  
  46.     def AbortNow(self, channel):
  47.         print("Device Respond Error!")
  48.         return
  49.    
  50.     def ReadReg(self, channel, reg):
  51.         got = None
  52.         if(self.porthandles[channel] != None):
  53.             commstr[0] = 0x60 | reg
  54.            
  55.             #got = self.porthandles[channel].write(commstr[0:1])
  56.             try:
  57.                 got = self.porthandles[channel].write(commstr[0:1])
  58.             except:
  59.                 self.AbortNow(channel)
  60.                 return 0
  61.            
  62.             commstr[0] = self.porthandles[channel].read(1)
  63.            
  64.             if(commstr[0] == b''):
  65.                 self.AbortNow(channel)
  66.                 return None
  67.            
  68.             """try:
  69.                commstr[0] = self.porthandles[channel].read(1)
  70.            except:
  71.                self.AbortNow(channel)
  72.                return 0"""
  73.            
  74.             if (got != 1):
  75.                 self.AbortNow(channel)
  76.                 return 0
  77.             else:
  78.                 return int.from_bytes(commstr[0], byteorder='big')
  79.         else:
  80.             return 0
  81.  
  82.     def WriteReg(self, channel, reg, data):
  83.         got = None
  84.         if(self.porthandles[channel] != None):
  85.             commstr[0] = 0x20 | reg
  86.             commstr[1] = data
  87.            
  88.             try:
  89.                 got = self.porthandles[channel].write(commstr[0:2])
  90.                 #print(got)
  91.             except:
  92.                 self.AbortNow(channel)
  93.            
  94.             if (got != 2):
  95.                 self.AbortNow(channel)
  96.     def Delay(self, c):
  97.         c //= 2; #takes about 2ms to do a single read over the USB
  98.         if (c <= 0):
  99.             c=1;
  100.         for i in range(c):
  101.             self.ReadReg(0,cREVRaddr)
  102.  
  103.     def ValidateByte(self, c):
  104.         if (c < 0):
  105.             return 0
  106.         elif (c > 255):
  107.             return 255
  108.         else:
  109.             return c
  110.  
  111.     def SetTrigMaster(self, channel, master):
  112.         if(self.porthandles[channel] != None):
  113.             readbyte = self.ReadReg(channel, cSUR1addr);
  114.             if (master != 0):
  115.                 readbyte = (readbyte | 0x40);
  116.             else:
  117.                 readbyte = (readbyte & 0xBF);
  118.                
  119.             self.WriteReg(channel, 0, readbyte);
  120.            
  121.     def SetClockMaster(self, channel, master):
  122.         if(self.porthandles[channel] != None):
  123.             readbyte = self.ReadReg(channel, cSUR1addr);
  124.             if (master != 0):
  125.                 readbyte = (readbyte | 0x80);
  126.             else:
  127.                 readbyte = (readbyte & 0x7F);
  128.                
  129.             self.WriteReg(channel, 0, readbyte);
  130.            
  131.     def GetTriggeredStatus(self, channel): #the latched status
  132.         if(self.porthandles[channel] != None):
  133.             return(self.ReadReg(channel, cSR1addr) & 2) >> 1
  134.         else:
  135.             return 0
  136.        
  137.     def SetLEDMode(self, channel, mode): #0,1,2,3 as modes(off, slow blink, blink, all)
  138.         if(self.porthandles[channel] != None):
  139.             readbyte = self.ReadReg(channel, cMISCCRaddr)
  140.             self.WriteReg(channel, cMISCCRaddr, (readbyte & 0x9F) | ((mode & 3) * 0x20))
  141.  
  142.     def GetCount(self, channel):
  143.         temp = 0
  144.         if(self.porthandles[channel] != None):
  145.             temp |= self.ReadReg (channel, cX3Raddr)
  146.             temp <<= 8
  147.             temp |= self.ReadReg (channel, cX2Raddr)
  148.             temp <<= 8
  149.             temp |= self.ReadReg (channel, cX1Raddr)
  150.             temp <<= 8
  151.             temp |= self.ReadReg (channel, cX0Raddr)
  152.         return temp
  153.        
  154.     def SetPLL(self, channel, m, n, u, dly):
  155.         if(self.porthandles[channel] != None):
  156.             if ((m>0) and (n>0) and (u>0)):
  157.                 data = None
  158.                 temp = None
  159.                 bit = None
  160.                 pullbits = None
  161.                 fout = ratio = None
  162.                 OBMUX = FBSEL = FBDLY = XDLYSEL = None
  163.                
  164.                
  165.                 cMISCCR_pllsclkHI    = (1<<0)
  166.                 cMISCCR_pllsshiftHI  = (1<<1)
  167.                 cMISCCR_pllsdinHI    = (1<<2)
  168.                 cMISCCR_pllsupdateHI = (1<<3)
  169.                 cMISCCR_pllmodeHI    = (1<<4)
  170.  
  171.                 cMISCCR_pllsclkLO    = (0<<0)
  172.                 cMISCCR_pllsshiftLO  = (0<<1)
  173.                 cMISCCR_pllsdinLO    = (0<<2)
  174.                 cMISCCR_pllsupdateLO = (0<<3)
  175.                 cMISCCR_pllmodeLO    = (0<<4)
  176.                 #readbyte = self.ReadReg(channel, cSUR1addr)
  177.                 #self.WriteReg(channel, cSUR1addr, (UCHAR)(readbyte & 0xFE)) #stop run
  178.                
  179.                 #dont set mode to hi until AFTER all the config bits are shifted in to the dynamic
  180.                 #s/r reg, else can select a bunch of rubbish bits and stop the clock to the UART !!!!!
  181.                 data = self.ReadReg(channel, cMISCCRaddr)
  182.                 data &= 0xE0 #kill all config bits
  183.                 self.WriteReg(channel, cMISCCRaddr, (data | cMISCCR_pllmodeLO | cMISCCR_pllsshiftLO)) #set dynamic mode
  184.                 self.WriteReg(channel, cMISCCRaddr, (data | cMISCCR_pllmodeLO | cMISCCR_pllsshiftHI)) #ready to shift
  185.                 """ from PAPLUSPLLdynamicAN.pdf app note
  186.  
  187.                26     XDLYSEL Mask-programmable delay select MUX
  188.                25-22  FBDLY[3:0] Delay line tap select MUX
  189.                21-20  FBSEL[1:0] Feedback source MUX
  190.                19-17  OBMUX[2:0] "B" output MUX
  191.                16-15  OAMUX[1:0] "A" output MUX
  192.                14-13  OADIV[1:0] "A" output divider (/v)
  193.                12-11  OBDIV[1:0] "B" output divider (/u)
  194.                10-5   FBDIV[5:0] Feedback signal divider (/m)
  195.                4-0    FINDIV[4:0] Input clock driver (/n)
  196.  
  197.                Configuration Bits from log file:
  198.                FINDIV   n
  199.                FBDIV    m
  200.                OBDIV    u
  201.                OADIV    00b
  202.                OAMUX    00b
  203.                OBMUX    100b
  204.                FBSEL    01b
  205.                FBDLY    0000b
  206.                XDLYSEL  1b
  207.  
  208.                """
  209.                 OBMUX = 2
  210.                 FBSEL = 1
  211.                 FBDLY = 0
  212.                 #if (channel > 1):
  213.                 FBDLY = dly
  214.                
  215.                 XDLYSEL = 1
  216.                 fout = 12.5e6*m/(n*u)
  217.                 ratio = 12.5e6 / fout
  218.                
  219.                 #sniff out sub divisions of the base 12.5MHz input and dont use the VCO at all !
  220.                 if ((ratio >= 0.999999999) and (ratio <= 1.000000001)):
  221.                     OBMUX = 1
  222.                     u = 1
  223.                 if ((ratio >= 1.999999999) and (ratio <= 2.000000001)):
  224.                     OBMUX = 1
  225.                     u = 2
  226.                 if ((ratio >= 2.999999999) and (ratio <= 3.000000001)):
  227.                     OBMUX = 1
  228.                     u = 3
  229.                 if ((ratio >= 3.999999999) and (ratio <= 4.000000001)):
  230.                     OBMUX = 1
  231.                     u = 4
  232.                    
  233.                 n-=1
  234.                 m-=1
  235.                 u-=1
  236.                 pllbits = n | (m << 5) | (u << 11)
  237.                
  238.                 pllbits |= (OBMUX << 17) | (FBSEL << 20) | (FBDLY << 22) | (XDLYSEL << 26)
  239.                 for bit in range(0,27):
  240.                     temp = (data | cMISCCR_pllmodeLO | cMISCCR_pllsshiftHI | (cMISCCR_pllsdinHI if (pllbits & 1) else cMISCCR_pllsdinLO))
  241.                     self.WriteReg(channel, cMISCCRaddr, temp) #data bit
  242.                     self.WriteReg(channel, cMISCCRaddr, (temp | cMISCCR_pllsclkHI))#clock it
  243.                     self.WriteReg(channel, cMISCCRaddr, (temp | cMISCCR_pllsclkLO))
  244.                     pllbits >>= 1;
  245.                
  246.                 self.WriteReg(channel, cMISCCRaddr, (data | cMISCCR_pllmodeLO | cMISCCR_pllsshiftLO | cMISCCR_pllsupdateLO)) #disable shift
  247.                 self.WriteReg(channel, cMISCCRaddr, (data | cMISCCR_pllmodeLO | cMISCCR_pllsshiftHI | cMISCCR_pllsupdateHI)) #make it update
  248.                 self.WriteReg(channel, cMISCCRaddr, (data | cMISCCR_pllmodeHI | cMISCCR_pllsshiftLO | cMISCCR_pllsupdateLO)) #disable shift & update done, leave in dynamic mode
  249.  
  250.                 #self._WriteReg(channel, cSUR1addr, readbyte);      //start (or not!) run
  251.  
  252.     def SetAmplitude(self, channel, voltage):
  253.         if(self.porthandles[channel] != None):
  254.             if (voltage < 1.5):
  255.                 voltage = 1.5
  256.             elif (voltage > 5):
  257.                 voltage = 5
  258.             daccode = int((voltage-1.5)*255/(5-1.5))
  259.            
  260.             self.WriteReg (channel, cDACARaddr, 2)
  261.             self.WriteReg (channel, cDACDRaddr, self.ValidateByte(daccode))
  262.             self.Delay(12) #let dac & amp settle (time const is about 12ms)
  263.            
  264.     def SetRun(self, channel, State):#0=stop 1=run
  265.         if(self.porthandles[channel] != None):
  266.             readbyte = self.ReadReg(channel, cSUR1addr)
  267.             self.WriteReg (channel, cSUR1addr, ((readbyte & 0xFE) | (1 * (State!=0))))
  268.  
  269.     def SetArm(self, channel, State):#0=disarm 1=arm
  270.         if(self.porthandles[channel] != None):
  271.             readbyte = self.ReadReg(channel, cSUR1addr)
  272.             self.WriteReg (channel, cSUR1addr, ((readbyte & 0xFD) | (2 * (State!=0))))
  273.  
  274.     def SetTrigger(self, channel, State): #0=disable 1=trigger
  275.         if(self.porthandles[channel] != None):
  276.             readbyte = self.ReadReg(channel, cSUR1addr)
  277.             self.WriteReg (channel, cSUR1addr, ((readbyte & 0xDF) | (32 * (State!=0))))
  278.        
  279.     def SetExtClk(self, channel, State): #0=int 1=ext
  280.         if(self.porthandles[channel] != None):
  281.             readbyte = self.ReadReg(channel, cSUR1addr)
  282.             self.WriteReg (channel, cSUR1addr, ((readbyte & 0xFB) | (4 * (State!=0))))
  283.  
  284.     def SetExtGate(self, channel, State): #0=int 1=ext
  285.         if(self.porthandles[channel] != None):
  286.             readbyte = self.ReadReg(channel, cSUR1addr)
  287.             self.WriteReg (channel, cSUR1addr, ((readbyte & 0xF7) | (8 * (State!=0))))
  288.  
  289.     def SetExtGateMode(self, channel, Mode): #0=nn, 1=pn, 2=np, 3=pp
  290.         if(self.porthandles[channel] != None):
  291.             readbyte = self.ReadReg(channel, cSUR3addr)
  292.             self.WriteReg (channel, cSUR3addr, ((readbyte & 0xFC) | (1 * (Mode))))
  293.  
  294.     def SelIntClk(self, channel, Freq): #0=100M,1=10M,2=1M
  295.         if(self.porthandles[channel] != None):
  296.             readbyte = self.ReadReg(channel, cSUR3addr)
  297.             self.WriteReg (channel, cSUR3addr, ((readbyte & 0xE3) | (4 * (Freq))))
  298.  
  299.     def SelIntGate(self, channel, Gate): #0=100ms,1=1s,2=10s
  300.         if(self.porthandles[channel] != None):
  301.             readbyte = self.ReadReg(channel, cSUR3addr)
  302.             self.WriteReg (channel, cSUR3addr, ((readbyte & 0x1F) | (32 * (Gate))))
  303.            
  304.     def GetIntGateDone(self, channel):
  305.         if(self.porthandles[channel] != None):
  306.             readbyte = self.ReadReg(channel, cSR2addr)
  307.             return 1 if (readbyte & 2) else 0
  308.         else:
  309.             return 1
  310.        
  311.     def GetExtGateBits(self, channel):
  312.         if(self.porthandles[channel] != None):
  313.             readbyte = self.ReadReg(channel, cSR2addr)
  314.             return (readbyte >> 2);
  315.         else:
  316.             return 0
  317.        
  318.     def InitCount(self, channel, master):#1 to 4
  319.         self.WriteReg (channel, cSUR1addr, 0)
  320.         self.WriteReg (channel, cSUR2addr, 0)
  321.         self.WriteReg (channel, cSUR3addr, 0)
  322.  
  323.         #every port that gets opened, strobe the masters J1_6 pin to sync the new device & the existing ones
  324.         self.WriteReg (0, 1, 0x20)
  325.         self.WriteReg (0, 1, 0x24)
  326.         self.WriteReg (0, 1, 0x4)
  327.         self.WriteReg (0, 1, 0x24)
  328.  
  329.         self.SetClockMaster (channel,master)
  330.         self.SetLEDMode (channel, 1)
  331.  
  332. #from tool application (USBcount_Main.frm) not fully compatible
  333.     def SetRunMode(self, Mode):
  334.         if(Mode == 0):#stop
  335.             for p in range(self.devcnt):
  336.                 self.SetArm(p, 0)
  337.                 self.SetRun(p, 0)
  338.                 self.SetTrigger(p, 0)
  339.         elif(Mode == 1):#run
  340.             for p in range(self.devcnt):
  341.                 self.SetRun(p, 0)
  342.                 self.SetArm(p, 0)
  343.                 self.SetTrigger(p, 0)
  344.             for p in range(self.devcnt):
  345.                 self.SetRun(p, 1)
  346.                 self.SetArm(p, 1)          
  347.         elif(Mode == 2):#one shot
  348.             for p in range(self.devcnt):
  349.                 self.SetTrigger(p, 0)
  350.                 self.SetArm(p, 0)
  351.                 self.SetRun(p, 0)
  352.             for p in range(self.devcnt):
  353.                 self.SetRun(p, 1)
  354.                 self.SetArm(p, 1)
  355.                
  356.     def SetMeasurementType(self,channel, Mode, idx, edge): #Freq = 0 , Period = 1
  357.         if(Mode == 1):#period mode
  358.             self.SetExtClk(channel, 0) #use internal freq
  359.             self.SetExtGate(channel, 1)#external gating
  360.             self.SelIntClk(channel, idx)#0=100M,1=10M,2=1M
  361.             self.SetExtGateMode(channel, edge)#0=nn, 1=pn, 2=np, 3=pp
  362.         elif(Mode == 0):#freq mode
  363.             self.SetExtClk(channel, 1) #use external freq
  364.             self.SetExtGate(channel, 0)#internal gating
  365.             self.SelIntGate(channel, idx)#0=100ms,1=1s,2=10s
  366.            
  367.  
  368. if __name__ == "__main__":
  369.     USBcount50 = USBcount50()
  370.     #USBcount50.SetAmplitude(0,2.0)
  371.     USBcount50.SetMeasurementType(0,1,0,3)#Ch0,Freqmode,100ms gatetime,always0
  372.     USBcount50.SetClockMaster(0, 1)
  373.     USBcount50.SetTrigMaster(0, 1)
  374.     USBcount50.SetRunMode(1)
  375.    
  376.     while 1:
  377.         USBcount50.SetTrigger(0, 0)
  378.         USBcount50.SetTrigger(0, 1)
  379.         while 1:
  380.             num = USBcount50.GetExtGateBits(0)
  381.             #print(num)
  382.             if(num & 4 ):
  383.                 break
  384.         print((100000000/USBcount50.GetCount(0)))
  385.        
  386.         USBcount50.SetArm(0,0)
  387.         USBcount50.SetArm(0,1)
  388.  
  389.     #USBcount50.SetRunMode(0)
  390.     #USBcount50.SetLEDMode(0,3)
  391.  
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