`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif

module LedToggler( // @[:@3.2]
  input   clock, // @[:@4.4]
  input   reset, // @[:@5.4]
  input   io_nreset, // @[:@6.4]
  output  io_output // @[:@6.4]
);
  reg [31:0] _T_8; // @[LedToggler.scala 20:24:@9.4]
  reg [31:0] _RAND_0;
  reg  _T_11; // @[LedToggler.scala 21:24:@10.4]
  reg [31:0] _RAND_1;
  wire  _T_5; // @[LedToggler.scala 19:13:@8.4]
  wire  _T_13; // @[LedToggler.scala 23:13:@11.4]
  wire  _T_16; // @[LedToggler.scala 25:16:@14.6]
  wire [32:0] _T_18; // @[LedToggler.scala 27:14:@18.6]
  wire [32:0] _T_19; // @[LedToggler.scala 27:14:@19.6]
  wire [31:0] _T_20; // @[LedToggler.scala 27:14:@20.6]
  wire [31:0] _GEN_0; // @[LedToggler.scala 23:22:@12.4]
  wire  _GEN_1; // @[LedToggler.scala 23:22:@12.4]
  assign _T_5 = io_nreset == 1'h0; // @[LedToggler.scala 19:13:@8.4]
  assign _T_13 = _T_8 == 32'h0; // @[LedToggler.scala 23:13:@11.4]
  assign _T_16 = _T_11 == 1'h0; // @[LedToggler.scala 25:16:@14.6]
  assign _T_18 = _T_8 - 32'h1; // @[LedToggler.scala 27:14:@18.6]
  assign _T_19 = $unsigned(_T_18); // @[LedToggler.scala 27:14:@19.6]
  assign _T_20 = _T_19[31:0]; // @[LedToggler.scala 27:14:@20.6]
  assign _GEN_0 = _T_13 ? 32'h17d7840 : _T_20; // @[LedToggler.scala 23:22:@12.4]
  assign _GEN_1 = _T_13 ? _T_16 : _T_11; // @[LedToggler.scala 23:22:@12.4]
  assign io_output = _T_11;
`ifdef RANDOMIZE
  integer initvar;
  initial begin
    `ifndef verilator
      #0.002 begin end
    `endif
  `ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{$random}};
  _T_8 = _RAND_0[31:0];
  `endif // RANDOMIZE_REG_INIT
  `ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{$random}};
  _T_11 = _RAND_1[0:0];
  `endif // RANDOMIZE_REG_INIT
  end
`endif // RANDOMIZE
  always @(posedge clock) begin
    if (_T_5) begin
      _T_8 <= 32'h0;
    end else begin
      if (_T_13) begin
        _T_8 <= 32'h17d7840;
      end else begin
        _T_8 <= _T_20;
      end
    end
    if (_T_5) begin
      _T_11 <= 1'h1;
    end else begin
      if (_T_13) begin
        _T_11 <= _T_16;
      end
    end
  end
endmodule