test.v

module test(clk, rst_n);
    input clk, rst_n;
    reg STAR;
    localparam S0=0, S1=1;

    always @(rst_n==0) STAR <= S0;
    always @(posedge clk) if (rst_n==1)
        casex(STAR)
            S0: STAR <= S1;
            S1: STAR <= S0;
        endcase
endmodule