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- library ieee;
- use ieee.std_logic_1164.all;
- entity test_to_01 is
- end entity test_to_01;
- architecture rtl of test_to_01 is
- signal s_test_in : std_logic_vector(8 downto 0) := "UX01ZWLZ-";
- signal s_test_out : std_logic_vector(8 downto 0);
- begin
- s_test_out <= to_01(s_test_in);
- end architecture rtl;
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