em

module V_5_4(
	input clk,
	input SW0,
	output reg [3:0] OUT
    );

wire EN;
reg [2:0] counter = 0;
reg [25:0] Q = 26'b0;

always @(posedge clk)
begin
	if (EN)
		Q <= 26'b0;
	else
		Q <= Q + 1;
end

//assign EN = (Q == 26'd49999999);
assign EN = (Q == 26'd3);

always @ (posedge clk)
begin
	counter <= counter + 1;
end

assign OUT = (SW0) ? { counter , 1'b1 } : { counter , 1'b0 }