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rtomazini Jul 4th, 2019 86 Never
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  1. module mod4_seq(input q0,q1,u,clk,output reg d0,d1);
  2. begin
  3.     always @ (posedge clk);
  4.     begin
  5.         if(q1 == 0)
  6.             d1 <= 1;
  7.            
  8.         else
  9.             d1 <=0;
  10.            
  11.         case(~u);
  12.             if ( q0== 0 && q1 == 1);
  13.                 d0 <= 1;
  14.            
  15.             if ( q0== 1 && q1 == 0);
  16.                 d0 <= 0;
  17.         endcase
  18.        
  19.         case(u);
  20.             if ( q0== 0 && q1 == 0);
  21.                 d0 <= 1;
  22.            
  23.             if ( q0== 1 && q1 == 1);
  24.                 d0 <= 0;
  25.                 endcase
  26. endmodule
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