comblogic_tb.v

`include "comblogic.v"

`timescale 1us/1us
module comblogic_tb;

   // on testbenches, inputs are regs
   reg a;
   reg b;

   // on testbenches, outputs are wires
   wire out;

   comblogic CL1 (out, a, b);

   initial begin
      a = 0;
      b = 0;
      #10 a = 1; b = 0;
      #10 a = 0; b = 1;
      #10 a = 1; b = 1;
      #10 $finish;

   end // initial begin

   initial begin
      $monitor ("%t | a = %d | b = %d | out = %d", $time, a, b, out);
      $dumpfile("dump.vcd");
      $dumpvars();
   end // initial begin
endmodule