library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter_tb is
end entity;

architecture TB of counter_tb is

    component counter
    port(
	A	:out	std_logic;
	Di	:in	std_logic_vector (10 downto 0);
	clk	:in	std_logic;
	reset	:in	std_logic
    );
    end component;

    -- register counter ports as signals
    signal A:		std_logic;
    signal Di:		std_logic_vector (10 downto 0);
    signal clk:		std_logic;
    signal reset:	std_logic;

begin
    -- set as SST
    set: counter port map (A, Di, clk, reset);

    -- simulate hardware clock
    process
    begin
	clk <= '0';
	wait for 500000 ns;
	clk <= '1';
	wait for 500000 ns;
    end process;

    -- test metronome
    process
    begin
	-- 60bpm (1 beat per second) for 3s
	Di <= "01111101000";
	wait for 3000 ms;
	-- 120bpm (2 beats per second) for 1.5s
	Di <= "00111110100";
	wait for 1500 ms;
	-- reset
	reset <= '1';
	wait for 50 ns;
	-- again reset after a minimal period of time, should be triggered although not in clock
	reset <= '0';
    end process;
end;