4 Bit Adder

module adder4b(X, Y, CI, S, CO);
 input [3:0] X, Y;
 input  CI;

 output [3:0] S;
 output CO;
 wire w1, w2, w3;

 // instantiating 4 1-bit full adders in Verilog
 fulladder u1(X[0], Y[0], CI, S[0], w1);
 fulladder u2(X[1], Y[1], w1, S[1], w2);
 fulladder u3(X[2], Y[2], w2, S[2], w3);
 fulladder u4(X[3], Y[3], w3, S[3], CO);
endmodule

//Structural code for one bit full adder
module fulladder(X, Y, CI, S, CO);
  input X, Y, CI;
  output S, CO;
  wire w1,w2,w3;

  xor G1(w1, X, Y);
  xor G2(S, w1, CI);
  and G3(w2, w1, CI);
  and G4(w3, X, Y);
  or  G5(CO, w2, w3);
endmodule


module adder4b_test;
    reg [3:0] X;
    reg [3:0] Y;
    reg CI;
    wire [3:0] S;
    wire CO;

    // Instantiate the Unit Under Test (UUT)
    adder4b uut(
        .X(X),
        .Y(Y),
        .CI(CI),
        .S(S),
        .CO(CO)
    );

    initial begin
       // $dumpfile("adder4bit.vcd");
        //$dumpvars(0,adder4b_test);
        X = 4;
        Y = 4;
        CI= 1;
        #10;

        X = 4;
        Y = 4;
        CI= 0;
        #10;

        X = 15;
        Y = 7;
        CI= 0;
        #10;

        X = 10;
        Y = 01;
        CI= 0;
        #10;

        X = 10;
        Y = 10;
        CI= 1;
        #10;

        X = 15;
        Y = 15;
        CI= 0;
        #10;

        X = 15;
        Y = 15;
        CI= 1;
        #10;


    end

    initial begin
          $monitor("t=%4d X=%4b, Y=%4b, CI=%b, sum=%4b,cout=%b\n",$time,X,Y,CI,S,CO);
         end

endmodule