RuhaYesterday at 11:05 AM
Hello, @AlgoMiner ! With me at 0.71v(0.73 at programming) one BCU is good at 600MHz with core temp at 66min-69avg-73max, while the other is set to 590 and has temps between 70min-72avg-77max to get zero "below target" errors. May be slightly different with your hardware and your cooling solution, and a bit different with every individual board. Non-zero "below target" error rate wears the FPGA chip. The chips usually have redundancy(hidden logic cells) in their design, and some of the damaged cells may "cure" over time, but if you want that board alive for years to come the note "Recommended to run at 500-600 MHz at 0.7-0.71V" in the readme is for you.

Wolf9466Today at 1:48 AM
@Ruha Please don't think, you're not good at it - and misleading users. >.>
"May be slightly different with your hardware and your cooling solution, and a bit different with every individual board. Non-zero "below target" error rate wears the FPGA chip. "
No. All of my no.
The fuck is wrong with you?
Below target means it got the wrong answer - which, 99.999% of the damn time means that it's clocked such that the design made an error. You clocked a bit high - this isn't damaging - and yes, I can detail the exact technical reason for its occurrance when overclocking (if anyone cares, which usually isn't the case) - moral is, please stop.
Further, due to silicon lottery, some clocks may cause errors for one person, and not another with a different BCU.

TurboShaneToday at 1:51 AM
I'm so lost lol

Wolf9466Today at 1:54 AM
@TurboShane He's saying that the "below target" error, even if you get one per day, is damaging your BCU.
He's full of shit.

TurboShaneToday at 1:55 AM
Oh yeah that is ridiculous. Keep it around 1% or less just to maintain profit lol

Wolf9466Today at 1:55 AM
Further, no damage is occurring.

TurboShaneToday at 1:56 AM
No damage. Completely normal

Wolf9466Today at 1:56 AM
nodnods.
For the record:
Heat and voltage are the two things with which you can cause damage.

RuhaToday at 2:12 AM
@Wolf9466 That's what I know about it how to figure out the safe spot, when temperature and voltage do not cause errors. Please explain, I care. Just trying to learn and told my understanding of this. That's a big question still who's full of shit.

Wolf9466Today at 2:13 AM
Okay, very well:
Clocking works like this: the design is first off, the MOST important factor in how high it will clock without error. To see why, I'll describe how an error is caused:
In your design, you'll have points where your logic is what's called combinatorial - this means that it's expected to execute in a single clk, basically... from the posedge (0 -> 1) to the next posedge. If the clock ticks again BEFORE the electricity makes it from the inputs of that circuit to the outputs (remember that it doesn't teleport!) - you read garbage.
You've not hurt anything, but whatever you read off those output wires is total bullshit :stuck_out_tongue:
Temperature and voltage are what, in general, will cause damage. One often raises voltage with the intent of making a higher clock speed stable...
... however, this doesn't imply the clock caused any harm.
The voltage may have, however.
For detail, here: https://alchitry.com/blogs/tutorials/fpga-timing
Alchitry
FPGA Timing
Timing is a term used in digital circuits to refer to the time it takes a signal to propagate from one flip-flop, through some combinational logic, to the next flip-flop.
The example under the subtitle "Broken timing" will show you exactly what occurs here when you've got too much logic in a combinatorial circuit for your clock speed.
Maybe I was a bit hard on ya, @Ruha. I apologize for that - I suppose I've gotten jaded with all the folks around crypto being willfully ignorant and then spreading it like it's gospel. >.>

TurboShaneToday at 2:21 AM
:grinning:

Wolf9466Today at 2:27 AM
@Ruha Lemme know if you've any questions after you look at it.