library ieee;
use     ieee.std_logic_1164.all;
use     ieee.std_logic_unsigned.all;
use     ieee.std_logic_misc.all;

entity SERIAL_RX is
  generic (
    F_ZEGARA    :natural := 20000000;           -- czestotliwosc zegata w [Hz]
    L_BODOW     :natural := 9600;           -- predkosc nadawania w [bodach]
    B_SLOWA     :natural := 8;              -- liczba bitow slowa danych (5-8)
    B_STOPOW    :natural := 2;              -- liczba bitow stopu (1-2)
    N_RX        :boolean := FALSE;          -- negacja logiczna sygnalu szeregowego
    N_SLOWO     :boolean := FALSE           -- negacja logiczna slowa danych
  );
  port (
    R       :in  std_logic;                 -- sygnal resetowania
    C       :in  std_logic;                 -- zegar taktujacy
    RX      :in  std_logic;                 -- odebrany sygnal szeregowy
    SLOWO   :out std_logic_vector(B_SLOWA-1 downto 0);  -- odebrane slowo danych
    GOTOWE  :out std_logic                 -- flaga potwierdzenia odbioru
  );
end SERIAL_RX;

architecture behavioural of SERIAL_RX is

  signal   wejscie  :std_logic_vector(0 to 1);      -- podwojny rejestr sygnalu RX

  type     ETAP     is (CZEKANIE, START, DANA, STOP); -- lista etapow pracy odbiornika
  signal   stan     :ETAP;                  -- rejestr maszyny stanow odbiornika

  constant T        :positive := F_ZEGARA/L_BODOW-1;    -- czas jednego bodu - liczba takt?w zegara
  signal   l_czasu      :natural range 0 to T;          -- licznik czasu jednego bodu
  signal   l_bitow      :natural range 0 to B_SLOWA-1;
  signal   bufor        :std_logic_vector(B_SLOWA-1 downto 0);

begin

   process (R, C) is
   begin

     if (R='1') then
       wejscie  <= (others => '0');
       stan <= CZEKANIE;
       l_czasu  <= 0;
       SLOWO    <= (others => '0');
       GOTOWE   <= '0';

     elsif (rising_edge(C)) then

       GOTOWE     <= '0';
       wejscie(0) <= RX;
       if (N_RX = TRUE) then
         wejscie(0) <= not(RX);
       end if;
       wejscie(1) <= wejscie(0);

       case stan is

         when CZEKANIE =>
           l_czasu <= 0;
           if (wejscie(1)='0' and wejscie(0)='1') then
              stan   <= START;
           end if;

         when START =>
           if(l_czasu /= T/2) then
              l_czasu <= l_czasu + 1;
           else
              l_czasu <= 0;
              l_bitow <= 0;
              stan <= DANA;
           end if;

         when DANA =>
           if(l_czasu /= T) then
              l_czasu <= l_czasu + 1;
           else
               l_czasu <= 0;
               bufor(bufor'left) <= wejscie(1);
               bufor(bufor'left-1 downto 0) <= bufor(bufor'left downto 1);
              if(l_bitow < B_SLOWA - 1) then
                  l_bitow <= l_bitow + 1;
              else
                  stan <= STOP;
              end if;
           end if;

         when STOP =>

              SLOWO <= bufor;
              if(N_SLOWO) then
                SLOWO <= not(bufor);
             end if;

              if(not(bufor) = "00110001") then
                SLOWO <=  "00000001";
              elsif(not(bufor) = "00110010") then
                SLOWO <=  "00000010";
              elsif(not(bufor) = "00110011") then
                SLOWO <=  "00000100";
              elsif(not(bufor) = "00110100") then
                SLOWO <=  "00001000";
              elsif(not(bufor) = "00110101") then
                SLOWO <=  "00010000";
              elsif(not(bufor) = "00110110") then
                SLOWO <=  "00100000";
              elsif(not(bufor) = "00110111") then
                SLOWO <=  "01000000";
              elsif(not(bufor) = "00111000") then
                SLOWO <=  "10000000";
              end if;

              GOTOWE <= '1';
              stan <= CZEKANIE;
       end case;

     end if;

   end process;

end behavioural;


--- MAIN FILE --- fpga.vhd ---
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
-- SubModule LD
-- Created   02/17/2016 9:41:04 PM
--------------------------------------------------------------------------------
Library IEEE;
Use IEEE.Std_Logic_1164.all;
Use IEEE.std_logic_misc.all;
Use IEEE.Std_Logic_unsigned.all;
Use IEEE.numeric_std.all;

entity FPGA is port
   (
     RS_TX : out  STD_LOGIC;
     RS_RX : in STD_LOGIC;
     CLK_I    : in  STD_LOGIC;
     RESET    : in  STD_LOGIC;
     BTN_IN  : in  STD_LOGIC_VECTOR(4 downto 0);
     SW_IN  : in  STD_LOGIC_VECTOR(7 downto 0);
     LED_OUT : out STD_LOGIC_VECTOR(7 downto 0)
   );
end FPGA;

--------------------------------------------------------------------------------

architecture Behavioural of FPGA is

  signal   R     : std_logic;
  signal   DRX   : std_logic_vector(7 downto 0);
  signal   DTX   : std_logic_vector(7 downto 0);
  signal   JEST  : std_logic;
  signal   INPUT : std_logic_vector(7 downto 0);
  signal   READY : std_logic;
  signal   MY_ERROR : std_logic;
begin

  --RS_TX <= RS_RX;

  sd :entity work.SERIAL_RX
  generic map (
    F_ZEGARA        => 20000000,           -- czestotliwosc zegata w [Hz]
    L_BODOW         => 9600,               -- minimalna predkosc nadawania w [bodach]
    B_SLOWA         => 8,              -- liczba bitow slowa danych (5-8)
    B_STOPOW        => 2,             -- liczba bitow stopu (1-2)
    N_RX            => TRUE,          -- negacja logiczna sygnalu szeregowego
    N_SLOWO         => TRUE           -- negacja logiczna slowa danych
  )
  port map(
    R               => R,                 -- sygnal resetowania
    C               => CLK_I,             -- zegar taktujacy
    RX              => RS_RX,             -- odebrany sygnal szeregowy
    SLOWO           => INPUT,
    GOTOWE          => READY
  );

  process (READY, INPUT) is
  begin
       if (READY = '1') then
       LED_OUT <= INPUT;
       end if;
  end process;

end Behavioural;