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LACI635

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LACI635
Apr 6th, 2020
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  1. ===================================================================
  2. MT7621 stage1 code Oct 28 2018 20:39:32 (ASIC)
  3. CPU=500000000 HZ BUS=166666666 HZ
  4. ==================================================================
  5. Change MPLL source from XTAL to CR...
  6. do MEMPLL setting..
  7. MEMPLL Config : 0x11100000
  8. 3PLL mode + External loopback
  9. === XTAL-40Mhz === DDR-1200Mhz ===
  10. PLL3 FB_DL: 0x11, 1/0 = 639/385 45000000
  11. PLL4 FB_DL: 0x11, 1/0 = 611/413 45000000
  12. PLL2 FB_DL: 0x15, 1/0 = 558/466 55000000
  13. do DDR setting..[01F40000]
  14. Apply DDR3 Setting...(use customer AC)
  15. 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
  16. --------------------------------------------------------------------------------
  17. 0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  18. 0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  19. 0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  20. 0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  21. 0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  22. 0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  23. 0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  24. 0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  25. 0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  26. 0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  27. 000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  28. 000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  29. 000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  30. 000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
  31. 000E:| 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
  32. 000F:| 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0
  33. 0010:| 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
  34. 0011:| 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
  35. 0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  36. 0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  37. 0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  38. 0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  39. 0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  40. 0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  41. 0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  42. 0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  43. 001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  44. 001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  45. 001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  46. 001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  47. 001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  48. 001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  49. DRAMC_DQSCTL1[0e0]=13000000
  50. DRAMC_DQSGCTL[124]=80000033
  51. rank 0 coarse = 15
  52. rank 0 fine = 64
  53. B:| 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0
  54. opt_dle value:10
  55. DRAMC_DDR2CTL[07c]=C287222D
  56. DRAMC_PADCTL4[0e4]=000022B3
  57. DRAMC_DQIDLY1[210]=0B0A0809
  58. DRAMC_DQIDLY2[214]=05090808
  59. DRAMC_DQIDLY3[218]=0B090808
  60. DRAMC_DQIDLY4[21c]=0A070C08
  61. DRAMC_R0DELDLY[018]=00001E1F
  62. ==================================================================
  63. RX DQS perbit delay software calibration
  64. ==================================================================
  65. 1.0-15 bit dq delay value
  66. ==================================================================
  67. bit| 0 1 2 3 4 5 6 7 8 9
  68. --------------------------------------
  69. 0 | 8 7 10 10 6 7 8 4 6 8
  70. 10 | 8 9 7 10 7 8
  71. --------------------------------------
  72.  
  73. ==================================================================
  74. 2.dqs window
  75. x=pass dqs delay value (min~max)center
  76. y=0-7bit DQ of every group
  77. input delay:DQS0 =31 DQS1 = 30
  78. ==================================================================
  79. bit DQS0 bit DQS1
  80. 0 (1~60)30 8 (1~56)28
  81. 1 (1~60)30 9 (1~59)30
  82. 2 (1~62)31 10 (1~58)29
  83. 3 (1~60)30 11 (1~56)28
  84. 4 (1~58)29 12 (1~58)29
  85. 5 (1~60)30 13 (1~56)28
  86. 6 (1~60)30 14 (1~60)30
  87. 7 (1~59)30 15 (1~56)28
  88. ==================================================================
  89. 3.dq delay value last
  90. ==================================================================
  91. bit| 0 1 2 3 4 5 6 7 8 9
  92. --------------------------------------
  93. 0 | 9 8 10 11 8 8 9 5 8 8
  94. 10 | 9 11 8 12 7 10
  95. ==================================================================
  96. ==================================================================
  97. TX perbyte calibration
  98. ==================================================================
  99. DQS loop = 15, cmp_err_1 = ffff0000
  100. dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1
  101. dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2
  102. DQ loop=15, cmp_err_1 = ffff0000
  103. dqs_perbyte_dly.last_dqdly_pass[0]=15, finish count=1
  104. dqs_perbyte_dly.last_dqdly_pass[1]=15, finish count=2
  105. byte:0, (DQS,DQ)=(8,8)
  106. byte:1, (DQS,DQ)=(8,8)
  107. DRAMC_DQODLY1[200]=88888888
  108. DRAMC_DQODLY2[204]=88888888
  109. 20,data:88
  110. [EMI] DRAMC calibration passed
  111.  
  112. ===================================================================
  113. MT7621 stage1 code done
  114. CPU=500000000 HZ BUS=166666666 HZ
  115. ===================================================================
  116.  
  117.  
  118. U-Boot 1.1.3 (May 8 2019 - 07:40:27)
  119.  
  120. Board: Ralink APSoC DRAM: 128 MB
  121. Power on memory test. Memory size= 128 MB...OK!
  122. relocate_code Pointer at: 87fb0000
  123.  
  124. Config XHCI 40M PLL
  125. RT2880_RSTSTAT_REG 0xc0030000
  126. ***************************
  127. Board power on Occurred
  128. ***************************
  129. flash manufacture id: c8, device id 40 18
  130. find flash: GD25Q128C
  131. ============================================
  132. Ralink UBoot Version: 5.0.0.0
  133. --------------------------------------------
  134. ASIC MT7621A DualCore (MAC to MT7530 Mode)
  135. DRAM_CONF_FROM: Auto-Detection
  136. DRAM_TYPE: DDR3
  137. DRAM bus: 16 bit
  138. Xtal Mode=3 OCP Ratio=1/3
  139. Flash component: SPI Flash
  140. Date:May 8 2019 Time:07:40:27
  141. ============================================
  142. icache: sets:256, ways:4, linesz:32 ,total:32768
  143. dcache: sets:256, ways:4, linesz:32 ,total:32768
  144.  
  145. ##### The CPU freq = 880 MHZ ####
  146. estimate memory size =128 Mbytes
  147. #Reset_MT7530
  148. set LAN/WAN LLLLW
  149.  
  150. restore_defaults:1
  151.  
  152. Please choose the operation:
  153. 1: Load system code to SDRAM via TFTP.
  154. 2: Load system code then write to Flash via TFTP.
  155. 3: Boot system code via Flash (default).
  156. 4: Entr boot command line interface.
  157. 7: Load Boot Loader code then write to Flash via Serial.
  158. 9: Load Boot Loader code then write to Flash via TFTP. 0
  159. n3: System Boot system code via Flash.
  160. Booting System 1
  161. Erasing SPI Flash...
  162. raspi_erase: offs:30000 len:10000
  163. .
  164. Writing to SPI Flash...
  165. .
  166. done
  167. ## Booting image at bc180000 ...
  168. Image Name: MIPS OpenWrt Linux-5.4.28
  169. Image Type: MIPS Linux Kernel Image (lzma compressed)
  170. Data Size: 2432818 Bytes = 2.3 MB
  171. Load Address: 80001000
  172. Entry Point: 80001000
  173. Verifying Checksum ... OK
  174. Uncompressing Kernel Image ... OK
  175. Erasing SPI Flash...
  176. raspi_erase: offs:30000 len:10000
  177. .
  178. Writing to SPI Flash...
  179. .
  180. done
  181. commandline uart_en=1 factory_mode=0 mem=128m root=/dev/mtdblock9
  182. No initrd
  183. ## Transferring control to Linux (at address 80001000) ...
  184. ## Giving linux memsize in MB, 128
  185.  
  186. Starting kernel ...
  187.  
  188. [ 0.000000] Linux version 5.4.28 (builder@buildhost) (gcc version 8.4.0 (OpenWrt GCC 8.4.0 r12840-5c1d88a83f)) #0 SMP Sun Apr 5 16:54:22 2020
  189. [ 0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3
  190. [ 0.000000] printk: bootconsole [early0] enabled
  191. [ 0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc)
  192. [ 0.000000] OF: fdt: No chosen node found, continuing without
  193. [ 0.000000] Initrd not found or empty - disabling initrd
  194. [ 0.000000] VPE topology {2,2} total 4
  195. [ 0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
  196. [ 0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
  197. [ 0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
  198. [ 0.000000] Zone ranges:
  199. [ 0.000000] Normal [mem 0x0000000000000000-0x0000000007ffffff]
  200. [ 0.000000] HighMem empty
  201. [ 0.000000] Movable zone start for each node
  202. [ 0.000000] Early memory node ranges
  203. [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000007ffffff]
  204. [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff]
  205. [ 0.000000] OF: fdt: Error -11 processing FDT
  206. [ 0.000000] percpu: Embedded 14 pages/cpu s26704 r8192 d22448 u57344
  207. [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 32480
  208. [ 0.000000] Kernel command line: rootfstype=squashfs,jffs2
  209. [ 0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes, linear)
  210. [ 0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes, linear)
  211. [ 0.000000] Writing ErrCtl register=00049000
  212. [ 0.000000] Readback ErrCtl register=00049000
  213. [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
  214. [ 0.000000] Memory: 120744K/131072K available (5823K kernel code, 201K rwdata, 1252K rodata, 1288K init, 237K bss, 10328K reserved, 0K cma-reserved, 0K highmem)
  215. [ 0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
  216. [ 0.000000] rcu: Hierarchical RCU implementation.
  217. [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
  218. [ 0.000000] NR_IRQS: 256
  219. [ 0.000000] random: get_random_bytes called from start_kernel+0x340/0x55c with crng_init=0
  220. [ 0.000000] Kernel panic - not syncing: Failed to find mtk,mt7621-sysc node
  221. [ 0.000000] Rebooting in 1 seconds..
  222. [ 0.000000] Reboot failed -- System halted
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