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Aug 13th, 2013
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  1. #define SW_SDRAM_BASE 0x01c01000
  2. #define SW_SDRAM_BASE_LEN 0x100
  3.  
  4. #define SW_SDRAM_REG_HPCR_USB1 (0x250 + ((1 << 2) * 4))
  5. #define SW_SDRAM_REG_HPCR_USB2 (0x250 + ((1 << 2) * 5))
  6.  
  7. /* HPCR */
  8. #define SW_SDRAM_BP_HPCR_READ_CNT_EN 31
  9. #define SW_SDRAM_BP_HPCR_RWRITE_CNT_EN 30
  10. #define SW_SDRAM_BP_HPCR_COMMAND_NUM 8
  11. #define SW_SDRAM_BP_HPCR_WAIT_STATE 4
  12. #define SW_SDRAM_BP_HPCR_PRIORITY_LEVEL 2
  13. #define SW_SDRAM_BP_HPCR_ACCESS_EN 0
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