moje

module main(
    input wire clk,
    input wire reset,
    input wire btn2,
    input wire btn1,
    input wire btn0,
    output [4:0] ledg
);
parameter FAZA1 = 3'b000;
parameter FAZA21 = 3'b001;
parameter FAZA22 = 3'b010;

reg [4:0] led, led_next;
reg [2:0] state_reg, state_next;
integer counter, counter_next;
wire b0, b1, b2;
redge r2(
    .clk(clk),
    .reset(reset),
    .signal_in(btn2),
    .signal_out(b2));
redge r1(
    .clk(clk),
    .reset(reset),
    .signal_in(btn1),
    .signal_out(b1));
redge r0(
    .clk(clk),
    .reset(reset),
    .signal_in(btn0),
    .signal_out(b0));

always @(posedge clk, posedge reset) begin
    if(reset == 1) begin
        led <= 5'b00000;
        state_reg <= FAZA1;
        counter <= 0;
    end
    else begin
        led <= led_next;
        state_reg <= state_next;
        counter <= counter_next;
    end
end

always @(*) begin
    led_next = led;
    state_next = state_reg;
    counter_next = counter;
    case(state_reg)
        FAZA1: begin
            if(b2 == 1) begin
                if(led == 5'b00000 || 5'b10000)
                    led_next = 5'b00001;
                else led_next = {led[3:0], 1'b0};
            end
            if(b1 == 1) begin
                led_next = 5'b00000;
                state_next = FAZA21;
                //counter_next = 0;
            end
        end
        FAZA21: begin
            if(led == 5'b11111) state_next = FAZA22;
            else if(b2 == 1) begin
                led_next = {led[3:0], 1'b1};
            end
        end
        FAZA22: begin
            if(led == 5'b00000) state_next = FAZA21;
            else if(b2 == 1) begin
                led_next = {1'b0, led[4:1]};
            end
        end
    endcase
end
endmodule