#cpudef "Complex_CPU_Project"
{
	#bits 8

	#tokendef ALS
	{
        ADD = 0b01100
		ADC = 0b01101
        SUB = 0b01110
		SBC = 0b01111


		AND = 0b10010
		OR  = 0b10011
		XOR = 0b10100
		CMP = 0b10101


    }

	#tokendef J
	{
		JMP  = 0b1101
		JP   = 0b1101
		CALL = 0b1111

	}

	#tokendef REG
	{
		A = 0b00
		B = 0b01
		C = 0b10
		D = 0b11

	}

	#tokendef FLAGS
	{
		Z   = 0b0000
		Za  = 0b0001
		Zx  = 0b0010
		O   = 0b0011
		U   = 0b0100
		G   = 0b0101
		E   = 0b0110
		L   = 0b0111

		NZ  = 0b1000
		NZa = 0b1001
		NZx = 0b1010
		NO  = 0b1011
		NU  = 0b1100
		NG  = 0b1101
		NE  = 0b1110
		NL  = 0b1111
	}

	;MISC
	NOP								-> 0x00[7:0]
	RET								-> 0x01[7:0]
	PUSH AB							-> 0x04[7:0]
	PUSH CD							-> 0x05[7:0]
	PUSH {src}						-> 0x06[7:0] @ src[15:0]
	POP AB							-> 0x07[7:0]
	POP CD							-> 0x08[7:0]
	JMP {src}						-> 0x0A[7:0] @ src[15:0]
	JP {src}						-> 0x0A[7:0] @ src[15:0]
	JR {src}						-> 0x0B[7:0] @ (src - pc)[7:0]
	CALL {src}						-> 0x0C[7:0] @ src[15:0]
	HALT							-> 0x0F[7:0]
	HLT								-> 0x0F[7:0]



	;REG <- IMME
	LD {dest:REG}, {src}			-> 0x1[3:0] @ 0b00[1:0] @ dest[1:0] @ src[7:0]

	;REG <- ADDR
	LD {dest:REG}, ({src})			-> 0x1[3:0] @ 0b01[1:0] @ dest[1:0] @ src[15:0]

	;REG <- ADDR CD
	LD {dest:REG}, (CD)				-> 0x1[3:0] @ 0b10[1:0] @ dest[1:0]

	;REG <- ADDR CD+B
	LD {dest:REG}, (CD+B)			-> 0x1[3:0] @ 0b11[1:0] @ dest[1:0]


	;ADDR <- REG
	LD ({dest}), {src:REG}			-> 0x2[3:0] @ 0b01[1:0] @ src[1:0] @ dest[15:0]

	;ADDR CD <- REG
	LD (CD), {src:REG}				-> 0x2[3:0] @ 0b10[1:0] @ src[1:0]

	;ADDR CD+B <- REG
	LD (CD+B), {src:REG}			-> 0x2[3:0] @ 0b11[1:0] @ src[1:0]


	;ADDR <- IMME
	LD ({dest}), {src}				-> 0x34 @ src[7:0] @ dest[15:0]

	;ADDR <- ADDR
	LD ({dest}), ({src})			-> 0x35 @ src[15:0] @ dest[15:0]

	;ADDR <- ADDR CD
	LD ({dest}), (CD)				-> 0x36 @ dest[15:0]

	;ADDR <- ADDR CD+B
	LD ({dest}), (CD+B)				-> 0x37 @ dest[15:0]

	;ADDR CD <- IMME
	LD (CD), {src}					-> 0x38 @ src[7:0]

	;ADDR CD <- ADDR
	LD (CD), ({src})				-> 0x39 @ src[15:0]

	;ADDR CD <- ADDR CD+B
	LD (CD), (CD+B)					-> 0x3A

	;ADDR CD+B <- IMME
	LD (CD+B), {src}				-> 0x3B @ src[7:0]

	;ADDR CD+B <- ADDR
	LD (CD+B), ({src})				-> 0x3C @ src[15:0]

	;ADDR CD+B <- ADDR CD
	LD (CD+B), (CD)					-> 0x3D


	;REG <- REG
	LD A, B							-> 0x40
	LD A, C							-> 0x41
	LD A, D							-> 0x42
	LD B, A							-> 0x43
	LD B, C							-> 0x44
	LD B, D							-> 0x45
	LD C, A							-> 0x46
	LD C, B							-> 0x47
	LD C, D							-> 0x48
	LD D, A							-> 0x49
	LD D, B							-> 0x4A
	LD D, C							-> 0x4B


	;REG <- 16b IMME
	LD AB, {src}					-> 0x20 @ src[15:0]
	LD CD, {src}					-> 0x21 @ src[15:0]
	LD SP, {src}					-> 0x30 @ src[15:0]


	;I/O
	IN A, ({src})					-> 0x3E
	IN ({dest}), ({src})			-> 0x4C
	IN (CD+B), ({src})				-> 0x4E

	OUT ({src}), A					-> 0x3F
	OUT ({dest}), ({src})			-> 0x4D
	OUT ({src}), (CD+B)				-> 0x4F


	;AL stuff
	{al:ALS} A						-> al[4:0] @ 0b000[2:0]
	{al:ALS} B						-> al[4:0] @ 0b001[2:0]
	{al:ALS} C						-> al[4:0] @ 0b010[2:0]
	{al:ALS} D						-> al[4:0] @ 0b011[2:0]
	{al:ALS} ({src})				-> al[4:0] @ 0b100[2:0] @ src[15:0]
	{al:ALS} (CD)					-> al[4:0] @ 0b101[2:0]
	{al:ALS} (CD+B)					-> al[4:0] @ 0b110[2:0]
	{al:ALS} {src}					-> al[4:0] @ 0b111[2:0] @ src[7:0]

	INC A							-> 0x80
	INC B							-> 0x81
	INC C							-> 0x82
	INC D							-> 0x83
	INC ({src})						-> 0x84 @ src[15:0]
	INC (CD)						-> 0x85
	INC (CD+B)						-> 0x86

	DEC A							-> 0x88
	DEC B							-> 0x89
	DEC C							-> 0x8A
	DEC D							-> 0x8B
	DEC ({src})						-> 0x8C @ src[15:0]
	DEC (CD)						-> 0x8D
	DEC (CD+B)						-> 0x8E

	SFR A							-> 0xB0
	SFR B							-> 0xB1
	SFR C							-> 0xB2
	SFR D							-> 0xB3
	SFR ({src})						-> 0xB4 @ src[15:0]
	SFR (CD)						-> 0xB5
	SFR (CD+B)						-> 0xB6

	SFL A							-> 0xB8
	SFL B							-> 0xB9
	SFL C							-> 0xBA
	SFL D							-> 0xBB
	SFL ({src})						-> 0xBC @ src[15:0]
	SFL (CD)						-> 0xBD
	SFL (CD+B)						-> 0xBE


	;Jumps
	{jmp:J} {flag:FLAGS} {src}		-> jmp[3:0] @ flag[3:0] @ src[15:0]
	JR {flag:FLAGS} {src}			-> 0xE[3:0] @ flag[3:0] @ (src - pc)[7:0]

}