wire [51:0] ff_dout;

    wire [9:0] ff_write_count;


    **assign o_wbus_count[10*idx+9:10*idx] = wbus_count[idx]; // Convert from 2D to 1D vector.**

    // Uppermost 2 bits of 8MB Auter space must be 0's
    wire upper_adrs_match = 1'b1; //(i_wbus_addr[22:21] == 2'h0);

    // Write only one fifo by decoding 5 address bits.
    **wire wen = i_wbus_enable[idx] & i_wbus_wen & upper_adrs_match &
         & (i_wbus_addr[20:16] == i_wbus_fws[5*idx+4:5*idx]);**


    **wire almost_full_d = i_wbus_enable[idx] & ( ff_write_count > Almost_Full_Depth );**

    // partslib.v: Simple DFF with Clock enable e.
    dreg_clr #(1) dc_amf( .c( i_aur_clk ), .ar( i_rst ), .e( 1'b1 ), .d( almost_full_d ),
                          .q( almost_full[idx] ) );



    // 52 bits x 512, First Word Fall Through.

    g1_ipcat_wbus_client_fifo U_client_ff (
      .rst           ( i_rst              ), // input rst
      .wr_clk        ( i_aur_clk          ), // input wr_clk
      .din           ( ffdin              ), // input [51 : 0] din
      .wr_en         ( wen                ), // input wr_en
      .full          (),                     // output full
      .wr_data_count ( ff_write_count     ), // output [9 : 0] wr_data_count

      // The Client Port is connected to all the read signals

      .rd_clk        ( i_wbus_clk[idx]    ), // input rd_clk
      .rd_en         ( i_wbus_ren[idx]    ), // input rd_en
      .dout          ( ff_dout            ), // output [51 : 0] dout
      .empty         ( o_wbus_empty[idx]  ), // output empty
      .rd_data_count ( wbus_count[idx]    ), // output [9 : 0] rd_data_count
      .valid         ( o_wbus_valid[idx]  )  // output valid
    );


    // o_wbus_waddr is divided into 32 bit widths for convenience
    // even though only the lowest 19 bits are used.

    **assign o_wbus_waddr[`WBUSRANGE] = {13'h0, ff_dout[50:32]};
    assign o_wbus_wdata[`WBUSRANGE] = ff_dout[31:0];**


 end