when readS0 =>
                if amiga_risingedge = '1' then      -- Rising edge of S0
                    oTG68_RW   <='1';                 -- Pull /RW high to indicate read cycle
						  iTG68_FCn	<= FC;
						  iTG68_SIZp <= "10";
						  U5_U7_1oen_o        <=    '0';             -- Enable address bus|                                                                            ----------------------
                    amiga_addr <= cpu_addr(23 downto 0); -- Drive a valid address on the address bus
                    mystate<=readS1;
                end if;

            when readS1 =>
                if amiga_fallingedge = '1' then              -- Falling edge of S1
                    oTG68_ASn    <=    '0';           -- Pull /AS low to indicate that a valid address is on the bus
                    oTG68_DSn    <=    '0';           -- Pull /USD,/LDS low|
                    mystate<=readS2;
                end if;

            when readS2 =>
                if amiga_risingedge = '1' then        -- Rising edge of S2                                                                      ----------------------
                    mystate<=readS3;
                end if;

            when readS3 =>
                if amiga_fallingedge = '1' then       -- Falling edge of S3
					  if DSACK ="00" or DSACK ="01" or DSACK ="10" then                -- Wait for cycle termination signal (DTACK) and inserts wait states
                    mystate<=readS4;
					  end if;
                end if;

            when readS4 =>
                if amiga_risingedge = '1' then        -- Rising edge of S4
							U4_2_U6_U7_2dir_o <= '0';                  -- Data Bus as input to FPGA|
							U4_2_U6_U7_2oen_o  <= '0';
							if cpu_addr(23 downto 20)=x"F" then
							cpu_datain<=ioTG68_DATA(15 downto 0);
							else
							cpu_datain<=ioTG68_DATA(31 downto 16);
							cpu_datain_temp <=ioTG68_DATA(15 downto 0);
							end if;
                   mystate<=readS5;
                end if;


            when readS5 =>
                if amiga_fallingedge = '1' then       -- Falling edge of S5
						  oTG68_ASn   <='1';                -- Negate /AS,/USD,/LDS|
                    oTG68_DSn   <='1';
--						  U5_U7_1oen_o     <= '1';            -- Disable address bus|
--                    amiga_addr  <= (others=>'Z');     -- Place Address bus in Hi-Z
                    mystate <= delay1;						  --                     |
                end if;