UART TX Verilog (115200bps)

module UART0 (CLOCK_50, UART_RXD, UART_TXD);

input CLOCK_50;

input UART_RXD;
output UART_TXD;

reg [7:0]   COUNT;
reg [7:0]   MAX = 8'b11011001;      //USED for 115200 CLOCK (217)
reg [7:0]   TXtemp = 8'b01001010;   //USED for TX Register Temp
reg [7:0]   RXtemp = 8'b00000000;   //USED for RX Register Temp
reg [3:0]   tx_cnt = 4'b0000;                       //USED for TX Register Count
reg             tx_enable = 1;              //USED to Enable Transmission
reg         tx_out = 1;

reg UART_CLK = 1'b0;

always @ (posedge CLOCK_50)
begin
    if(COUNT == MAX)
    begin
        COUNT <= 0;
        UART_CLK <= ~UART_CLK;
    end
    else
    begin
        COUNT = COUNT + 1;
    end
end


always @ (posedge UART_CLK)
begin

   if (tx_enable) begin

      if (tx_cnt == 0) begin
       tx_out <= 0;
     end

      if (tx_cnt > 0 && tx_cnt < 9) begin
        tx_out <= TXtemp[tx_cnt -1];
     end

      if (tx_cnt == 9) begin
       tx_out <= 1;
       tx_cnt <= 0;
     end

      tx_cnt <= tx_cnt + 1;
   end

end

assign UART_TXD = tx_out;

endmodule