Verilog

`timescale 1ns / 1ps

module test_bcd2sseg();

reg [3:0] t_sw;
wire [6:0] t_seg;

artix7_bcd DUT
(
    .sw(t_sw),
    .seg(t_seg)
);

initial begin

    $display("%0t: Starting TPG.", $time);

    //DLA 0
    #10 t_sw = 4'b0000;

    // check the results
    #1
    if(t_seg == 7'b0000001)
        $display("%0t Test PASSED for pattern %b", $time, t_sw);
    else
        $display("%0t Test FAILED for pattern %b - result is %b", $time,
    t_sw, t_seg);

    //DLA 1
    #10 t_sw = 4'b0001;

    // check the results
    #1
    if(t_seg == 7'b1001111)
        $display("%0t Test PASSED for pattern %b", $time, t_sw);
    else
        $display("%0t Test FAILED for pattern %b - result is %b", $time,
    t_sw, t_seg);

    //DLA 2
    #10 t_sw = 4'b0010;

    // check the results
    #1
    if(t_seg == 7'b0010010)
        $display("%0t Test PASSED for pattern %b", $time, t_sw);
    else
        $display("%0t Test FAILED for pattern %b - result is %b", $time,
    t_sw, t_seg);

    //DLA 3
    #10 t_sw = 4'b0011;

    // check the results
    #1
    if(t_seg == 7'b0000110)
        $display("%0t Test PASSED for pattern %b", $time, t_sw);
    else
        $display("%0t Test FAILED for pattern %b - result is %b", $time,
    t_sw, t_seg);

    //DLA 4
    #10 t_sw = 4'b0100;

    // check the results
    #1
    if(t_seg == 7'b1001100)
        $display("%0t Test PASSED for pattern %b", $time, t_sw);
    else
        $display("%0t Test FAILED for pattern %b - result is %b", $time,
    t_sw, t_seg);

    //DLA 5
    #10 t_sw = 4'b0101;

    // check the results
    #1
    if(t_seg == 7'b0100100)
        $display("%0t Test PASSED for pattern %b", $time, t_sw);
    else
        $display("%0t Test FAILED for pattern %b - result is %b", $time,
    t_sw, t_seg);

    //DLA 6
    #10 t_sw = 4'b0110;

    // check the results
    #1
    if(t_seg == 7'b0100000)
        $display("%0t Test PASSED for pattern %b", $time, t_sw);
    else
        $display("%0t Test FAILED for pattern %b - result is %b", $time,
    t_sw, t_seg);

    //DLA 7
    #10 t_sw = 4'b0111;

    // check the results
    #1
    if(t_seg == 7'b0001111)
        $display("%0t Test PASSED for pattern %b", $time, t_sw);
    else
        $display("%0t Test FAILED for pattern %b - result is %b", $time,
    t_sw, t_seg);

    //DLA 8
    #10 t_sw = 4'b1000;

    // check the results
    #1
    if(t_seg == 7'b0000000)
        $display("%0t Test PASSED for pattern %b", $time, t_sw);
    else
        $display("%0t Test FAILED for pattern %b - result is %b", $time,
    t_sw, t_seg);

    //DLA 9
    #10 t_sw = 4'b1001;

    // check the results
    #1
    if(t_seg == 7'b0000100)
        $display("%0t Test PASSED for pattern %b", $time, t_sw);
    else
        $display("%0t Test FAILED for pattern %b - result is %b", $time,
    t_sw, t_seg);




     #10 $display("%0t: Finished TPG.", $time);
     $stop;
 end
 endmodule