// in_buffer would need to be a power of 2 long if this filter were to run indefinitely, but it looks like x_bus is input data and only contains 100 samples?

// you cannot initialize ram in a reset like you are.  Ram needs to be accessed one address at a time.  You
// are clearing all memory locations at once.  The synthesis tool has no choice but to use a huge amount
// of registers as memory so it can clear them all at the same time.  If you remove this initialization
// you may be back to inferring ram properly.  You are in luck because all BRAM is initialized to zero
// https://www.xilinx.com/support/documentation/application_notes/xapp463.pdf pg 11
// I do not infer ram like this so I am not sure if your inference will continue to work or not.
// I do not think the synthesis tool will infer a block ram without a write enable and read enable...i could be wrong though
// this design will probably have sketchy timing without using the BRAM and multiplier of the FPGA.

// why are you clipping adjust?.

// Instead of a state machine, using a simple counter may be slicker (although a bit more difficult to read and prob take
// some simulation to nail all the required actions to occur on the correct counter value.
//
// e.g. some counter which counts from 0 to say 75...that is the 73 filter cycles + a few extra for prep/cleanup (you could
// get by with a counter from 0 to 72 if you really wanted to.

// forgive the ternary operators ( x <= y ? z : v), they can be changed to if elsif ... but ternary operators are more compact although harder to read.

always @(posedge clk)
begin
our_counter <= st ? 1 : our_counter > 0 && our_counter < 75 ? our_counter + 1 : 0;  // so create counter to count from 0 to 75 starting when st strobes (st must be single cycle strobe).  When counter reaches 75 reset to 0 and wait for st to strobe then repeat

// now all of our actions are based on this counter value

 x_ind <= reset ? 0 : our_counter == 75 ? x_ind + 1;               // we will increment x_ind after our filtering action (sometime after counter == 74)
 x_bus <= our_counter == 75 : x_bus + 1 : x_bus
 in_buffer[buf_head] <= x_bus;                                     // I dont thin
 buf_head <= reset ? 0 : counter == 73 ? buf_head + 1 : buf_head;
 buf_tail <= counter == 0 ? buf_head : buf_tail <= buf_tail - 1;   // reset buf_tail to buf_head at beginning and the decrement rest of the time.
 h_ind <= st ? 1 : h_ind > 0 && h_ind < 72 ? h_ind + 1 : 0;        // run h_ind from 0 to 72 on start (or maybe our_counter == 1)
 mul_x <= in_buffer[buf_tail]                                      //
 mul_h <= h_bus;
 pip_add <= mul_x * mul_h;                                         // we will always multiply mul_x and mul_y
 acc     <= reset ? 0 : our_counter == 0 ? 0 : acc + pip_add;      // reset accumulator at the beginning of each filter operation our_counter == 1 may be needed here
 outdata <= our_counter == 74 ? acc : outdata;                     // store accumulated value when it is available (maybe our_counter == 75)
 y_ram[m_addr] <= outdata;                                         // i think we need outdata as intermediate value if we have any hope of keeping y_ram as infered ram
 m_addr <= our_counter == 74 ? m_addr + 1 : m_addr;

 // i may have forgot some signals and some of the our_counter values may be off by a clock cycle or two but hopefully you get the idea on an alternate way of doing this

end