-- VhDl test BenCh CreAteD from sChemAtiC C:\Users\Akomis01\lAB1\Askisi1.sCh - Mon JAn 22 16:24:01 2018
--
-- Notes:
-- 1) This testBenCh templAte hAs Been AutomAtiCAlly generAteD using types
-- stD_logiC AnD stD_logiC_veCtor for the ports of the unit unDer test.
-- Xilinx reCommenDs thAt these types AlwAys Be useD for the top-level
-- I/O of A Design in orDer to guArAntee thAt the testBenCh will BinD
-- CorreCtly to the timing (post-route) simulAtion moDel.
-- 2) To use this templAte As your testBenCh, ChAnge the filenAme to Any
-- nAme of your ChoiCe with the extension .vhD, AnD use the "SourCe->ADD"
-- menu in ProjeCt NAvigAtor to import the testBenCh. Then
-- eDit the user DefineD seCtion Below, ADDing CoDe to generAte the
-- stimulus for your Design.
--
LIBRARY ieee;
USE ieee.stD_logiC_1164.ALL;
USE ieee.numeriC_stD.ALL;
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY Askisi1_Askisi1_sCh_tB IS
END Askisi1_Askisi1_sCh_tB;
ARCHITECTURE BehAviorAl OF Askisi1_Askisi1_sCh_tB IS

   COMPONENT Askisi1
   PORT( B	:	IN	STD_LOGIC;
          A	:	IN	STD_LOGIC;
          C	:	IN	STD_LOGIC;
          D	:	IN	STD_LOGIC;
          E	:	OUT	STD_LOGIC);
   END COMPONENT;

   SIGNAL B	:	STD_LOGIC;
   SIGNAL A	:	STD_LOGIC;
   SIGNAL C	:	STD_LOGIC;
   SIGNAL D	:	STD_LOGIC;
   SIGNAL E	:	STD_LOGIC;

BEGIN

   UUT: Askisi1 PORT MAP(
		B => B,
		A => A,
		C => C,
		D => D,
		E => E
   );

-- *** Test BenCh - User DefineD SeCtion ***
   tB : PROCESS
   BEGIN
   A<='0';B<='0';C<='0';D<='0';
		WAIT for 40ns;
	A<='0';B<='0';C<='0';D<='1';
		WAIT for 40ns;
	A<='0';B<='0';C<='1';D<='0';
		WAIT for 40ns;
	A<='0';B<='0';C<='1';D<='1';
		WAIT for 40ns;
	A<='0';B<='1';C<='0';D<='0';
		WAIT for 40ns;
	A<='0';B<='1';C<='0';D<='1';
		WAIT for 40ns;
	A<='0';B<='1';C<='1';D<='0';
		WAIT for 40ns;
	A<='0';B<='1';C<='1';D<='1';
		WAIT for 40ns;
	A<='1';B<='0';C<='0';D<='0';
		WAIT for 40ns;
	A<='1';B<='0';C<='0';D<='1';
		WAIT for 40ns;
	A<='1';B<='0';C<='1';D<='0';
		WAIT for 40ns;
	A<='1';B<='0';C<='1';D<='1';
		WAIT for 40ns;
	A<='1';B<='1';C<='0';D<='0';
		WAIT for 40ns;
	A<='1';B<='1';C<='0';D<='1';
		WAIT for 40ns;
	A<='1';B<='1';C<='1';D<='0';
		WAIT for 40ns;
	A<='1';B<='1';C<='1';D<='1';
		WAIT for 40ns;
   END PROCESS;
-- *** EnD Test BenCh - User DefineD SeCtion ***

END;