CPE212-[Lab8.1] q1

module ALU1Bit(y,z,a,b,ci,c);
    input a,b,ci;
    input [1:0]c;
    output y,z;
    wire s,co;          //y0,0
    wire anda;          //y0,1
    wire nota;          //y1,0

    wire xorab;         //z1,1

    reg x;

    FullAdder fa1(s,co,a,b,ci); //y0,0
    and and1(anda,a,b);         //y0,1
    not not1(nota,a);           //y1,0

    xor xor1(xorab,a,b);        //z1,1

    Mux4to1 mux1(y,s,anda,nota,1'b0,c);
    Mux4to1 mux2(z,co,x,x,xorab,c);

endmodule

module FullAdder(s,co,a,b,ci);
    input a,b,ci;
    output s,co;
    wire xorab,andaci,andbci;

    xor xor1(xorab,a,b);
    xor xor2(s,xorab,ci);

    and and1(andaci,xorab,ci);
    and and2(andbci,b,a);

    or or1(co,andaci,andbci);
endmodule

module Mux4to1(o,i1,i2,i3,i4,c);
    input i1,i2,i3,i4;
    input [1:0]c;
    output o;

    wire andi1,andi2,andi3,andi4;

    input [1:0]nc;

    not not1(nc[0],c[0]);
    not not2(nc[1],c[1]);

    and and1(andi1,i1,nc[1],nc[0]);
    and and2(andi2,i2,nc[1],c[0]);
    and and3(andi3,i3,c[1],nc[0]);
    and and4(andi4,i4,c[1],c[0]);

    or or1(o,andi1,andi2,andi3,andi4);
endmodule

module stimulus;
    reg a,b,ci;
    reg [1:0]c;
    wire y,z;

    ALU1Bit alu1bit(y,z,a,b,ci,c);

    initial
        begin
            a = 1'b0;
            b = 1'b0;
            ci = 1'b0;
            c = 1'b0;
        end
    always      #10 a = ~a;
    always      #20 b = ~b;
    always      #40 c[0] = ~c[0];
    always      #80 c[1] = ~c[1];
    always      #5  ci = ~ci;

    initial #155 $finish;

    initial
        $monitor($time,"\tc = %b\ta = %d\tb = %d\tci = %d\ty = %d\tz = %d",c,a,b,ci,y,z);

endmodule