beesnotincluded

Auto VHDL testbench generator

Mar 20th, 2012
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  1. #!/usr/bin/perl
  2. # Author: Chris Cross
  3. # URL: http://www.beesnotincluded.com
  4. # License: GPLv2
  5. # Status: Underdevelopment
  6.  
  7.  
  8. use feature ':5.10';
  9. say "Auto VHDL Test bench generator 1.0";
  10.  
  11.  
  12. #Process command line arguments
  13. if(int(@ARGV) >= 1){
  14.     $infile = $ARGV[0];   #First argument is input vhdl file
  15.  
  16.    if(int(@ARGV) >= 2) {    #Second argument is output vhdl file
  17.         $outfile = $ARGV[1];
  18.     } else {
  19.         $outfile = $ARGV[0];
  20.         $outfile =~ s/\.vhdl*$/_tb.vhd/;
  21.     }
  22. } else {
  23.     say "Usage: $0 infile.vhd [outfile.vhd]";
  24.     exit -1;
  25. }
  26. say "Generating testbench for file:\t", $infile;
  27. say "Writing testbench to file:\t", $outfile;
  28.  
  29. open my $vhdlfile, $infile or say "Can't open $infile" and exit -1;
  30.  
  31. my @pnames = ();        #stores port names
  32. my @ptypes = ();        #stores port types (std_logic, std_logic_vector)
  33. my @pdirs = ();         #stores
  34. my @pcomments = ();     #sotres eol comments associated with ports
  35. my $entity = "";        #stores entity name
  36. my $architecture = "";  #stores architecture name
  37. my @includes = ();      #stores any library includes
  38.  
  39.  
  40. my $line;               #
  41. while ($line = <$vhdlfile>){
  42.  
  43.     #Search for ports
  44.     if($line =~ /(\w+)\s*:\s*(INOUT|IN|OUT)\s*([^;-]+)\s*[;-]\s*-*\s*(.*)/i) {
  45.         #store the signal name in the appropriate array
  46.         push(@pnames, $1);
  47.         push(@pcomments, $4);
  48.  
  49.         #Strip trailing whitespace
  50.         my $type = $3;
  51.         $type =~s/\s+$//;
  52.         push(@ptypes, $type);
  53.  
  54.         #Deduce the port type
  55.         if($2 =~ /IN/i) {
  56.             push(@pdir, "IN");
  57.         }
  58.         elsif($2 =~ /OUT/i) {
  59.             push(@pdir, "OUT");
  60.         }
  61.         elsif($2 =~ /INOUT/i) {
  62.             push(@pdir, "INOUT");
  63.         }
  64.     # Search for entity name
  65.     } elsif($line =~ /entity\s*(\w+)\s*is/i) {
  66.         $entity = $1;
  67.     # Search for architecture type
  68.     } elsif($line =~ /architecture\s*(\w+)\s*of/i) {
  69.         $architecture = $1;
  70.     # Search for library or use statements
  71.     } elsif($line =~ /^(use|library).*/i) {
  72.         $line =~s/\s*$//;
  73.         push(@includes, $line);
  74.     }  
  75. }
  76.  
  77. #Open the output file
  78. open $tbfile, '>', $outfile or say "Can't open $outfile" and exit -1;
  79.  
  80. #Write header text
  81. print $tbfile "--\t**************************************************************\n";
  82. print $tbfile "--\tAuto-generated testbench for design entity: $entity\n";
  83. print $tbfile "--\tGenerated on: ".localtime() , "\n";
  84. print $tbfile "--\t**************************************************************\n\n";
  85.  
  86. #Write library imports necessary for tesbench
  87. print $tbfile "-- Library includes\n";
  88. foreach my $stmt (@includes){
  89.     print $tbfile $stmt, "\n";
  90. }
  91. print $tbfile "\n";
  92.  
  93. #Create useful variables
  94. $entity_tb = $entity . "_tb";
  95.  
  96.  
  97. #Write entity declaration for testbench
  98. print $tbfile "-- Entity declaration\n";
  99. print $tbfile "entity $entity_tb is\n";
  100. print $tbfile "end entity $entity_tb;\n\n";
  101.  
  102. #Write architecture for test bench
  103. print $tbfile "-- Architecture definition\n";
  104. print $tbfile "architecture sim of $entity_tb is\n";
  105.  
  106. #Write the signal declarations
  107. print $tbfile "-- Signal declarations\n";
  108. for (my $i = 0; $i < int(@pnames); $i++) {
  109.     print $tbfile "\tsignal ", $pnames[$i], "\t: ", $ptypes[$i], "; --", $pcomments[$i], "\n";
  110. }
  111.  
  112. #print placeholder for testbench signal declarations
  113. print $tbfile "-- Testbench signal declarations\n\n";
  114.  
  115. print $tbfile "begin\n";
  116.  
  117. #Instantiate the component
  118. print $tbfile "-- Component declarations\n";
  119. print $tbfile 'dut : entity work.',$entity,'(',$architecture,') port map(', "\n";
  120. for (my $i = 0; $i < int(@pnames); $i++) {
  121.     my $ending = ",\n";
  122.     if($i == @pnames-1) {
  123.         $ending = "\n";
  124.     }
  125.     print $tbfile "\t", $pnames[$i], "\t=>", $pnames[$i], $ending;
  126. }
  127. print $tbfile ");\n";
  128.  
  129. #End architecture
  130. print $tbfile "end architecture sim;";
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