library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity licznik is
	port(
		dir 	: in std_logic;
		clk1s 	: in std_logic;
		clk01s 	: in std_logic;
		ena 	: in std_logic;
		reset 	: in std_logic;
		L 	: out std_logic_vector(3 downto 0)
		);
end licznik;
	--slug
architecture clock of licznik is
	signal licznik_reg : unsigned(3 downto 0);
begin
	process(dir, clk1s, clk01s, reset)
	begin
		if (ena = '1') then
			if(reset = '1')then
				licznik_reg <= unsigned(VAL_START);
			elsif(rising_edge(clk1s))then
				if (dir = '1') then
					licznik_reg <= licznik_reg + 1;
				elsif (dir = '0') then
					licznik_reg <= licznik_reg - 1;
				end if;
			end if;
		end if;
	end process;
	L <= std_logic_vector(licznik_reg);
end clock;