library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity IBDECODER is
    Port ( I : in  STD_LOGIC_VECTOR(31 downto 0);
           ALU_OP : out  STD_LOGIC_VECTOR(5 downto 0);
           select_shamt : out  STD_LOGIC;
			  select_imm : out STD_LOGIC;
			  select_b : out STD_LOGIC;
			  extend_sign : out STD_LOGIC;
			  extend_msb : out STD_LOGIC);
end IBDECODER;

architecture Behavioral of IBDECODER is

signal t_select : STD_LOGIC;
signal sign : STD_LOGIC;

begin
	ALU_Op <= I(5 downto 0) when I(31 downto 26) = "000000" else I(31 downto 26);
	extend_msb <= I(15);

sign <=
'0' when I(31 downto 26) = X"0" and I(5 downto 0) = X"20" else 		-- add
'1' when I(31 downto 26) = X"8" else											-- addi
'1' when I(31 downto 26) = X"9" else											-- addiu
'0' when I(31 downto 26) = X"0" and I(5 downto 0) = X"21" else			-- addu
'0' when I(31 downto 26) = X"0" and I(5 downto 0) = X"24" else			-- and

'0' when I(31 downto 26) = X"C" else											-- andi
'0' when I(31 downto 26) = X"4" else											-- beq
'0' when I(31 downto 26) = X"5" else											-- bne
'0' when I(31 downto 26) = X"2" else											-- j
'0' when I(31 downto 26) = X"3" else											-- jal

'0' when I(31 downto 26) = X"0" and I(5 downto 0) = X"8" else			-- jr
'1' when I(31 downto 26) = X"24" else											-- lbu
'1' when I(31 downto 26) = X"25" else											-- lhu
'1' when I(31 downto 26) = X"30" else											-- ll
'0' when I(31 downto 26) = X"F" else											-- lui

'1' when I(31 downto 26) = X"23" else											-- lw
'0' when I(31 downto 26) = X"0" and I(5 downto 0) = X"27" else			-- nor
'0' when I(31 downto 26) = X"0" and I(5 downto 0) = X"25" else			-- or
'0' when I(31 downto 26) = X"D" else											-- ori
'0' when I(31 downto 26) = X"0" and I(5 downto 0) = X"2A" else			-- slt

'1' when I(31 downto 26) = X"A" else											-- slti
'1' when I(31 downto 26) = X"B" else											-- sltiu
'0' when I(31 downto 26) = X"0" and I(5 downto 0) = X"2B" else			-- sltu
'0' when I(31 downto 26) = X"0" and I(5 downto 0) = X"00" else			-- sll
'0' when I(31 downto 26) = X"0" and I(5 downto 0) = X"02" else			-- srl

'1' when I(31 downto 26) = X"28" else											-- sb
'1' when I(31 downto 26) = X"38" else											-- sc
'1' when I(31 downto 26) = X"29" else											-- sh
'1' when I(31 downto 26) = X"2B" else											-- sw
'0' when I(31 downto 26) = X"0" and I(5 downto 0) = X"22" else			-- sub

'0' when I(31 downto 26) = X"0" and I(5 downto 0) = X"23";				-- subu

-- ############################
t_select <= '0' when I(31 downto 26) = X"0" else '1';
select_imm <= t_select;
select_b <= t_select;
select_shamt <= '1' when I(31 downto 26) = X"0" and (I(5 downto 0) = X"0" or I(5 downto 0) = X"2");

-- ############################

end Behavioral;