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  1.  
  2. AtmelStart.elf: file format elf32-littlearm
  3.  
  4. Sections:
  5. Idx Name Size VMA LMA File off Algn
  6. 0 .text 00000324 00000000 00000000 00010000 2**2
  7. CONTENTS, ALLOC, LOAD, READONLY, CODE
  8. 1 .relocate 00000000 20000000 20000000 00010324 2**0
  9. CONTENTS
  10. 2 .lpram 00000000 30000000 30000000 00010324 2**0
  11. CONTENTS
  12. 3 .bss 0000001c 20000000 20000000 00020000 2**2
  13. ALLOC
  14. 4 .stack 00002004 2000001c 2000001c 00020000 2**0
  15. ALLOC
  16. 5 .ARM.attributes 00000028 00000000 00000000 00010324 2**0
  17. CONTENTS, READONLY
  18. 6 .comment 00000059 00000000 00000000 0001034c 2**0
  19. CONTENTS, READONLY
  20. 7 .debug_info 00004c12 00000000 00000000 000103a5 2**0
  21. CONTENTS, READONLY, DEBUGGING
  22. 8 .debug_abbrev 000010cb 00000000 00000000 00014fb7 2**0
  23. CONTENTS, READONLY, DEBUGGING
  24. 9 .debug_loc 000004c3 00000000 00000000 00016082 2**0
  25. CONTENTS, READONLY, DEBUGGING
  26. 10 .debug_aranges 00000168 00000000 00000000 00016545 2**0
  27. CONTENTS, READONLY, DEBUGGING
  28. 11 .debug_ranges 00000178 00000000 00000000 000166ad 2**0
  29. CONTENTS, READONLY, DEBUGGING
  30. 12 .debug_macro 00003dbe 00000000 00000000 00016825 2**0
  31. CONTENTS, READONLY, DEBUGGING
  32. 13 .debug_line 00005406 00000000 00000000 0001a5e3 2**0
  33. CONTENTS, READONLY, DEBUGGING
  34. 14 .debug_str 00080c48 00000000 00000000 0001f9e9 2**0
  35. CONTENTS, READONLY, DEBUGGING
  36. 15 .debug_frame 000001f0 00000000 00000000 000a0634 2**2
  37. CONTENTS, READONLY, DEBUGGING
  38.  
  39. Disassembly of section .text:
  40.  
  41. 00000000 <exception_table>:
  42. 0: 20 20 00 20 41 02 00 00 3d 02 00 00 3d 02 00 00 . A...=...=...
  43. ...
  44. 2c: 3d 02 00 00 00 00 00 00 00 00 00 00 3d 02 00 00 =...........=...
  45. 3c: 3d 02 00 00 3d 02 00 00 3d 02 00 00 3d 02 00 00 =...=...=...=...
  46. 4c: 3d 02 00 00 3d 02 00 00 3d 02 00 00 3d 02 00 00 =...=...=...=...
  47. 5c: 3d 02 00 00 3d 02 00 00 3d 02 00 00 3d 02 00 00 =...=...=...=...
  48. 6c: 3d 02 00 00 3d 02 00 00 3d 02 00 00 3d 02 00 00 =...=...=...=...
  49. 7c: 3d 02 00 00 3d 02 00 00 3d 02 00 00 3d 02 00 00 =...=...=...=...
  50. ...
  51. 94: 3d 02 00 00 3d 02 00 00 3d 02 00 00 3d 02 00 00 =...=...=...=...
  52. a4: 3d 02 00 00 3d 02 00 00 3d 02 00 00 00 00 00 00 =...=...=.......
  53.  
  54. 000000b4 <__do_global_dtors_aux>:
  55. b4: b510 push {r4, lr}
  56. b6: 4c06 ldr r4, [pc, #24] ; (d0 <__do_global_dtors_aux+0x1c>)
  57. b8: 7823 ldrb r3, [r4, #0]
  58. ba: 2b00 cmp r3, #0
  59. bc: d107 bne.n ce <__do_global_dtors_aux+0x1a>
  60. be: 4b05 ldr r3, [pc, #20] ; (d4 <__do_global_dtors_aux+0x20>)
  61. c0: 2b00 cmp r3, #0
  62. c2: d002 beq.n ca <__do_global_dtors_aux+0x16>
  63. c4: 4804 ldr r0, [pc, #16] ; (d8 <__do_global_dtors_aux+0x24>)
  64. c6: e000 b.n ca <__do_global_dtors_aux+0x16>
  65. c8: bf00 nop
  66. ca: 2301 movs r3, #1
  67. cc: 7023 strb r3, [r4, #0]
  68. ce: bd10 pop {r4, pc}
  69. d0: 20000000 .word 0x20000000
  70. d4: 00000000 .word 0x00000000
  71. d8: 00000324 .word 0x00000324
  72.  
  73. 000000dc <frame_dummy>:
  74. dc: 4b08 ldr r3, [pc, #32] ; (100 <frame_dummy+0x24>)
  75. de: b510 push {r4, lr}
  76. e0: 2b00 cmp r3, #0
  77. e2: d003 beq.n ec <frame_dummy+0x10>
  78. e4: 4907 ldr r1, [pc, #28] ; (104 <frame_dummy+0x28>)
  79. e6: 4808 ldr r0, [pc, #32] ; (108 <frame_dummy+0x2c>)
  80. e8: e000 b.n ec <frame_dummy+0x10>
  81. ea: bf00 nop
  82. ec: 4807 ldr r0, [pc, #28] ; (10c <frame_dummy+0x30>)
  83. ee: 6803 ldr r3, [r0, #0]
  84. f0: 2b00 cmp r3, #0
  85. f2: d100 bne.n f6 <frame_dummy+0x1a>
  86. f4: bd10 pop {r4, pc}
  87. f6: 4b06 ldr r3, [pc, #24] ; (110 <frame_dummy+0x34>)
  88. f8: 2b00 cmp r3, #0
  89. fa: d0fb beq.n f4 <frame_dummy+0x18>
  90. fc: 4798 blx r3
  91. fe: e7f9 b.n f4 <frame_dummy+0x18>
  92. 100: 00000000 .word 0x00000000
  93. 104: 20000004 .word 0x20000004
  94. 108: 00000324 .word 0x00000324
  95. 10c: 00000324 .word 0x00000324
  96. 110: 00000000 .word 0x00000000
  97.  
  98. 00000114 <_oscctrl_init_sources>:
  99. }
  100.  
  101. static inline void hri_oscctrl_write_OSC16MCTRL_reg(const void *const hw, hri_oscctrl_osc16mctrl_reg_t data)
  102. {
  103. OSCCTRL_CRITICAL_SECTION_ENTER();
  104. ((Oscctrl *)hw)->OSC16MCTRL.reg = data;
  105. 114: 2282 movs r2, #130 ; 0x82
  106. 116: 4b0b ldr r3, [pc, #44] ; (144 <_oscctrl_init_sources+0x30>)
  107.  
  108. /**
  109. * \brief Initialize clock sources
  110. */
  111. void _oscctrl_init_sources(void)
  112. {
  113. 118: b510 push {r4, lr}
  114. 11a: 751a strb r2, [r3, #20]
  115. while (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg) {
  116. 11c: 4a0a ldr r2, [pc, #40] ; (148 <_oscctrl_init_sources+0x34>)
  117. 11e: 2002 movs r0, #2
  118. 120: 0011 movs r1, r2
  119. 122: 7814 ldrb r4, [r2, #0]
  120. 124: 4204 tst r4, r0
  121. 126: d1fc bne.n 122 <_oscctrl_init_sources+0xe>
  122. #endif
  123. #endif
  124.  
  125. #if CONF_OSC16M_CONFIG == 1
  126. #if CONF_OSC16M_ENABLE == 1
  127. while (!hri_oscctrl_get_STATUS_OSC16MRDY_bit(hw))
  128. 128: 2210 movs r2, #16
  129. return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_OSC16MRDY) >> OSCCTRL_STATUS_OSC16MRDY_Pos;
  130. 12a: 68d8 ldr r0, [r3, #12]
  131. 12c: 4210 tst r0, r2
  132. 12e: d0fc beq.n 12a <_oscctrl_init_sources+0x16>
  133. ((Oscctrl *)hw)->OSC16MCTRL.reg |= OSCCTRL_OSC16MCTRL_ONDEMAND;
  134. 130: 2080 movs r0, #128 ; 0x80
  135. 132: 7d1a ldrb r2, [r3, #20]
  136. 134: 4302 orrs r2, r0
  137. 136: 751a strb r2, [r3, #20]
  138. while (((Oscctrl *)hw)->DPLLSYNCBUSY.reg & reg) {
  139. 138: 230e movs r3, #14
  140. 13a: 780a ldrb r2, [r1, #0]
  141. 13c: 421a tst r2, r3
  142. 13e: d1fc bne.n 13a <_oscctrl_init_sources+0x26>
  143. #if CONF_OSC16M_ONDEMAND == 1
  144. hri_oscctrl_set_OSC16MCTRL_ONDEMAND_bit(hw);
  145. #endif
  146. #endif
  147. (void)hw;
  148. }
  149. 140: bd10 pop {r4, pc}
  150. 142: 46c0 nop ; (mov r8, r8)
  151. 144: 40000c00 .word 0x40000c00
  152. 148: 40000c38 .word 0x40000c38
  153.  
  154. 0000014c <_oscctrl_init_referenced_generators>:
  155. #if CONF_DFLL_CONFIG == 1
  156. while (hri_gclk_read_SYNCBUSY_reg(GCLK))
  157. ;
  158. #endif
  159. (void)hw, (void)tmp;
  160. }
  161. 14c: 4770 bx lr
  162. ...
  163.  
  164. 00000150 <_init_chip>:
  165. }
  166.  
  167. static inline void hri_nvmctrl_set_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask)
  168. {
  169. NVMCTRL_CRITICAL_SECTION_ENTER();
  170. ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_RWS(mask);
  171. 150: 2002 movs r0, #2
  172.  
  173. /**
  174. * \brief Initialize the hardware abstraction layer
  175. */
  176. void _init_chip(void)
  177. {
  178. 152: b510 push {r4, lr}
  179. 154: 4a08 ldr r2, [pc, #32] ; (178 <_init_chip+0x28>)
  180. 156: 6853 ldr r3, [r2, #4]
  181. 158: 4303 orrs r3, r0
  182. 15a: 6053 str r3, [r2, #4]
  183. hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE);
  184.  
  185. _set_performance_level(2);
  186. 15c: 4b07 ldr r3, [pc, #28] ; (17c <_init_chip+0x2c>)
  187. 15e: 4798 blx r3
  188.  
  189. _osc32kctrl_init_sources();
  190. 160: 4b07 ldr r3, [pc, #28] ; (180 <_init_chip+0x30>)
  191. 162: 4798 blx r3
  192. _oscctrl_init_sources();
  193. 164: 4b07 ldr r3, [pc, #28] ; (184 <_init_chip+0x34>)
  194. 166: 4798 blx r3
  195. _mclk_init();
  196. 168: 4b07 ldr r3, [pc, #28] ; (188 <_init_chip+0x38>)
  197. 16a: 4798 blx r3
  198. #if _GCLK_INIT_1ST
  199. _gclk_init_generators_by_fref(_GCLK_INIT_1ST);
  200. #endif
  201. _oscctrl_init_referenced_generators();
  202. 16c: 4b07 ldr r3, [pc, #28] ; (18c <_init_chip+0x3c>)
  203. 16e: 4798 blx r3
  204. _gclk_init_generators_by_fref(_GCLK_INIT_LAST);
  205. 170: 20ff movs r0, #255 ; 0xff
  206. 172: 4b07 ldr r3, [pc, #28] ; (190 <_init_chip+0x40>)
  207. 174: 4798 blx r3
  208. #endif
  209.  
  210. #if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3)
  211. _port_event_init();
  212. #endif
  213. }
  214. 176: bd10 pop {r4, pc}
  215. 178: 41004000 .word 0x41004000
  216. 17c: 00000195 .word 0x00000195
  217. 180: 00000219 .word 0x00000219
  218. 184: 00000115 .word 0x00000115
  219. 188: 000001b9 .word 0x000001b9
  220. 18c: 0000014d .word 0x0000014d
  221. 190: 000001cd .word 0x000001cd
  222.  
  223. 00000194 <_set_performance_level>:
  224. }
  225.  
  226. static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
  227. {
  228. uint8_t tmp;
  229. tmp = ((Pm *)hw)->PLCFG.reg;
  230. 194: 2380 movs r3, #128 ; 0x80
  231. tmp = (tmp & PM_PLCFG_PLSEL(mask)) >> PM_PLCFG_PLSEL_Pos;
  232. 196: 2103 movs r1, #3
  233. tmp = ((Pm *)hw)->PLCFG.reg;
  234. 198: 05db lsls r3, r3, #23
  235. 19a: 789a ldrb r2, [r3, #2]
  236. /**
  237. * \brief Set performance level
  238. */
  239. void _set_performance_level(const uint8_t level)
  240. {
  241. if (hri_pm_get_PLCFG_PLSEL_bf(PM, PM_PLCFG_PLSEL_Msk) != level) {
  242. 19c: 400a ands r2, r1
  243. 19e: 4290 cmp r0, r2
  244. 1a0: d009 beq.n 1b6 <_set_performance_level+0x22>
  245. ((Pm *)hw)->INTFLAG.reg = mask;
  246. 1a2: 22ff movs r2, #255 ; 0xff
  247. 1a4: 719a strb r2, [r3, #6]
  248.  
  249. static inline void hri_pm_write_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t data)
  250. {
  251. uint8_t tmp;
  252. PM_CRITICAL_SECTION_ENTER();
  253. tmp = ((Pm *)hw)->PLCFG.reg;
  254. 1a6: 789a ldrb r2, [r3, #2]
  255. tmp &= ~PM_PLCFG_PLSEL_Msk;
  256. tmp |= PM_PLCFG_PLSEL(data);
  257. 1a8: 4008 ands r0, r1
  258. tmp &= ~PM_PLCFG_PLSEL_Msk;
  259. 1aa: 438a bics r2, r1
  260. tmp |= PM_PLCFG_PLSEL(data);
  261. 1ac: 4310 orrs r0, r2
  262. ((Pm *)hw)->PLCFG.reg = tmp;
  263. 1ae: 7098 strb r0, [r3, #2]
  264. return ((Pm *)hw)->INTFLAG.reg;
  265. 1b0: 799a ldrb r2, [r3, #6]
  266. hri_pm_clear_INTFLAG_reg(PM, 0xFF);
  267. hri_pm_write_PLCFG_PLSEL_bf(PM, level);
  268. while (!hri_pm_read_INTFLAG_reg(PM))
  269. 1b2: 2a00 cmp r2, #0
  270. 1b4: d0fc beq.n 1b0 <_set_performance_level+0x1c>
  271. ;
  272. }
  273. }
  274. 1b6: 4770 bx lr
  275.  
  276. 000001b8 <_mclk_init>:
  277. }
  278.  
  279. static inline void hri_mclk_write_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t data)
  280. {
  281. MCLK_CRITICAL_SECTION_ENTER();
  282. ((Mclk *)hw)->BUPDIV.reg = data;
  283. 1b8: 2208 movs r2, #8
  284. 1ba: 4b03 ldr r3, [pc, #12] ; (1c8 <_mclk_init+0x10>)
  285. 1bc: 719a strb r2, [r3, #6]
  286. ((Mclk *)hw)->LPDIV.reg = data;
  287. 1be: 3a04 subs r2, #4
  288. 1c0: 715a strb r2, [r3, #5]
  289. ((Mclk *)hw)->CPUDIV.reg = data;
  290. 1c2: 3a03 subs r2, #3
  291. 1c4: 711a strb r2, [r3, #4]
  292. {
  293. void *hw = (void *)MCLK;
  294. hri_mclk_write_BUPDIV_reg(hw, MCLK_BUPDIV_BUPDIV(CONF_MCLK_BUPDIV));
  295. hri_mclk_write_LPDIV_reg(hw, MCLK_LPDIV_LPDIV(CONF_MCLK_LPDIV));
  296. hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_CPUDIV(CONF_MCLK_CPUDIV));
  297. }
  298. 1c6: 4770 bx lr
  299. 1c8: 40000400 .word 0x40000400
  300.  
  301. 000001cc <_gclk_init_generators_by_fref>:
  302.  
  303. void _gclk_init_generators_by_fref(uint32_t bm)
  304. {
  305.  
  306. #if CONF_GCLK_GENERATOR_0_CONFIG == 1
  307. if (bm & (1ul << 0)) {
  308. 1cc: 07c3 lsls r3, r0, #31
  309. 1ce: d506 bpl.n 1de <_gclk_init_generators_by_fref+0x12>
  310. }
  311.  
  312. static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
  313. {
  314. GCLK_CRITICAL_SECTION_ENTER();
  315. ((Gclk *)hw)->GENCTRL[index].reg = data;
  316. 1d0: 4a03 ldr r2, [pc, #12] ; (1e0 <_gclk_init_generators_by_fref+0x14>)
  317. 1d2: 4b04 ldr r3, [pc, #16] ; (1e4 <_gclk_init_generators_by_fref+0x18>)
  318. 1d4: 621a str r2, [r3, #32]
  319. while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
  320. 1d6: 4a04 ldr r2, [pc, #16] ; (1e8 <_gclk_init_generators_by_fref+0x1c>)
  321. 1d8: 6859 ldr r1, [r3, #4]
  322. 1da: 4211 tst r1, r2
  323. 1dc: d1fc bne.n 1d8 <_gclk_init_generators_by_fref+0xc>
  324. | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos)
  325. | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos)
  326. | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE);
  327. }
  328. #endif
  329. }
  330. 1de: 4770 bx lr
  331. 1e0: 00010106 .word 0x00010106
  332. 1e4: 40001800 .word 0x40001800
  333. 1e8: 000007fd .word 0x000007fd
  334.  
  335. 000001ec <main>:
  336. #include <atmel_start.h>
  337.  
  338. int main(void)
  339. {
  340. /* Initializes MCU, drivers and middleware */
  341. atmel_start_init();
  342. 1ec: 4b07 ldr r3, [pc, #28] ; (20c <main+0x20>)
  343. {
  344. 1ee: b510 push {r4, lr}
  345. atmel_start_init();
  346. 1f0: 4798 blx r3
  347. ((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask);
  348. }
  349.  
  350. static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask)
  351. {
  352. ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
  353. 1f2: 23c0 movs r3, #192 ; 0xc0
  354. 1f4: 22f0 movs r2, #240 ; 0xf0
  355.  
  356. static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index,
  357. hri_port_wrconfig_reg_t data)
  358. {
  359. PORT_CRITICAL_SECTION_ENTER();
  360. ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
  361. 1f6: 4906 ldr r1, [pc, #24] ; (210 <main+0x24>)
  362. 1f8: 4806 ldr r0, [pc, #24] ; (214 <main+0x28>)
  363. ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask;
  364. 1fa: 05db lsls r3, r3, #23
  365. 1fc: 609a str r2, [r3, #8]
  366. ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data;
  367. 1fe: 6288 str r0, [r1, #40] ; 0x28
  368. 200: 20c0 movs r0, #192 ; 0xc0
  369. 202: 0600 lsls r0, r0, #24
  370. 204: 6288 str r0, [r1, #40] ; 0x28
  371. ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask;
  372. 206: 61da str r2, [r3, #28]
  373. 208: e7fd b.n 206 <main+0x1a>
  374. 20a: 46c0 nop ; (mov r8, r8)
  375. 20c: 000002b1 .word 0x000002b1
  376. 210: 40002800 .word 0x40002800
  377. 214: 400000f0 .word 0x400000f0
  378.  
  379. 00000218 <_osc32kctrl_init_sources>:
  380. calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw);
  381. hri_osc32kctrl_write_OSCULP32K_reg(hw,
  382. #if CONF_OSC32K_CALIB_ENABLE == 1
  383. OSC32KCTRL_OSCULP32K_CALIB(CONF_OSC32K_CALIB)
  384. #else
  385. OSC32KCTRL_OSCULP32K_CALIB(calib)
  386. 218: 21f8 movs r1, #248 ; 0xf8
  387. }
  388.  
  389. static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw)
  390. {
  391. uint32_t tmp;
  392. tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg;
  393. 21a: 4b04 ldr r3, [pc, #16] ; (22c <_osc32kctrl_init_sources+0x14>)
  394. 21c: 0149 lsls r1, r1, #5
  395. 21e: 69da ldr r2, [r3, #28]
  396. 220: 400a ands r2, r1
  397. }
  398.  
  399. static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data)
  400. {
  401. OSC32KCTRL_CRITICAL_SECTION_ENTER();
  402. ((Osc32kctrl *)hw)->OSCULP32K.reg = data;
  403. 222: 61da str r2, [r3, #28]
  404. ((Osc32kctrl *)hw)->RTCCTRL.reg = data;
  405. 224: 2201 movs r2, #1
  406. 226: 611a str r2, [r3, #16]
  407. ;
  408. #endif
  409. #endif
  410. hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL));
  411. (void)calib;
  412. }
  413. 228: 4770 bx lr
  414. 22a: 46c0 nop ; (mov r8, r8)
  415. 22c: 40001000 .word 0x40001000
  416.  
  417. 00000230 <system_init>:
  418. #include <peripheral_clk_config.h>
  419. #include <utils.h>
  420. #include <hal_init.h>
  421.  
  422. void system_init(void)
  423. {
  424. 230: b510 push {r4, lr}
  425. * Currently the following initialization functions are supported:
  426. * - System clock initialization
  427. */
  428. static inline void init_mcu(void)
  429. {
  430. _init_chip();
  431. 232: 4b01 ldr r3, [pc, #4] ; (238 <system_init+0x8>)
  432. 234: 4798 blx r3
  433. init_mcu();
  434. }
  435. 236: bd10 pop {r4, pc}
  436. 238: 00000151 .word 0x00000151
  437.  
  438. 0000023c <Dummy_Handler>:
  439.  
  440. /**
  441. * \brief Default interrupt handler for unused IRQs.
  442. */
  443. void Dummy_Handler(void)
  444. {
  445. 23c: e7fe b.n 23c <Dummy_Handler>
  446. ...
  447.  
  448. 00000240 <Reset_Handler>:
  449. if (pSrc != pDest) {
  450. 240: 4811 ldr r0, [pc, #68] ; (288 <Reset_Handler+0x48>)
  451. 242: 4912 ldr r1, [pc, #72] ; (28c <Reset_Handler+0x4c>)
  452. {
  453. 244: b570 push {r4, r5, r6, lr}
  454. if (pSrc != pDest) {
  455. 246: 4288 cmp r0, r1
  456. 248: d004 beq.n 254 <Reset_Handler+0x14>
  457. 24a: 2300 movs r3, #0
  458. for (; pDest < &_erelocate;) {
  459. 24c: 4c10 ldr r4, [pc, #64] ; (290 <Reset_Handler+0x50>)
  460. 24e: 18ca adds r2, r1, r3
  461. 250: 42a2 cmp r2, r4
  462. 252: d313 bcc.n 27c <Reset_Handler+0x3c>
  463. *pDest++ = 0;
  464. 254: 2100 movs r1, #0
  465. 256: 4b0f ldr r3, [pc, #60] ; (294 <Reset_Handler+0x54>)
  466. for (pDest = &_szero; pDest < &_ezero;) {
  467. 258: 4a0f ldr r2, [pc, #60] ; (298 <Reset_Handler+0x58>)
  468. 25a: 4293 cmp r3, r2
  469. 25c: d312 bcc.n 284 <Reset_Handler+0x44>
  470. SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk);
  471. 25e: 21ff movs r1, #255 ; 0xff
  472. 260: 4b0e ldr r3, [pc, #56] ; (29c <Reset_Handler+0x5c>)
  473. 262: 4a0f ldr r2, [pc, #60] ; (2a0 <Reset_Handler+0x60>)
  474. 264: 438b bics r3, r1
  475. 266: 6093 str r3, [r2, #8]
  476. NVMCTRL->CTRLB.bit.MANW = 1;
  477. 268: 2380 movs r3, #128 ; 0x80
  478. 26a: 4a0e ldr r2, [pc, #56] ; (2a4 <Reset_Handler+0x64>)
  479. 26c: 6851 ldr r1, [r2, #4]
  480. 26e: 430b orrs r3, r1
  481. 270: 6053 str r3, [r2, #4]
  482. __libc_init_array();
  483. 272: 4b0d ldr r3, [pc, #52] ; (2a8 <Reset_Handler+0x68>)
  484. 274: 4798 blx r3
  485. main();
  486. 276: 4b0d ldr r3, [pc, #52] ; (2ac <Reset_Handler+0x6c>)
  487. 278: 4798 blx r3
  488. 27a: e7fe b.n 27a <Reset_Handler+0x3a>
  489. *pDest++ = *pSrc++;
  490. 27c: 58c5 ldr r5, [r0, r3]
  491. 27e: 3304 adds r3, #4
  492. 280: 6015 str r5, [r2, #0]
  493. 282: e7e4 b.n 24e <Reset_Handler+0xe>
  494. *pDest++ = 0;
  495. 284: c302 stmia r3!, {r1}
  496. 286: e7e8 b.n 25a <Reset_Handler+0x1a>
  497. 288: 00000324 .word 0x00000324
  498. 28c: 20000000 .word 0x20000000
  499. 290: 20000000 .word 0x20000000
  500. 294: 20000000 .word 0x20000000
  501. 298: 2000001c .word 0x2000001c
  502. 29c: 00000000 .word 0x00000000
  503. 2a0: e000ed00 .word 0xe000ed00
  504. 2a4: 41004000 .word 0x41004000
  505. 2a8: 000002bd .word 0x000002bd
  506. 2ac: 000001ed .word 0x000001ed
  507.  
  508. 000002b0 <atmel_start_init>:
  509.  
  510. /**
  511. * Initializes MCU, drivers and middleware in the project
  512. **/
  513. void atmel_start_init(void)
  514. {
  515. 2b0: b510 push {r4, lr}
  516. system_init();
  517. 2b2: 4b01 ldr r3, [pc, #4] ; (2b8 <atmel_start_init+0x8>)
  518. 2b4: 4798 blx r3
  519. }
  520. 2b6: bd10 pop {r4, pc}
  521. 2b8: 00000231 .word 0x00000231
  522.  
  523. 000002bc <__libc_init_array>:
  524. 2bc: b570 push {r4, r5, r6, lr}
  525. 2be: 2600 movs r6, #0
  526. 2c0: 4d0c ldr r5, [pc, #48] ; (2f4 <__libc_init_array+0x38>)
  527. 2c2: 4c0d ldr r4, [pc, #52] ; (2f8 <__libc_init_array+0x3c>)
  528. 2c4: 1b64 subs r4, r4, r5
  529. 2c6: 10a4 asrs r4, r4, #2
  530. 2c8: 42a6 cmp r6, r4
  531. 2ca: d109 bne.n 2e0 <__libc_init_array+0x24>
  532. 2cc: 2600 movs r6, #0
  533. 2ce: f000 f819 bl 304 <_init>
  534. 2d2: 4d0a ldr r5, [pc, #40] ; (2fc <__libc_init_array+0x40>)
  535. 2d4: 4c0a ldr r4, [pc, #40] ; (300 <__libc_init_array+0x44>)
  536. 2d6: 1b64 subs r4, r4, r5
  537. 2d8: 10a4 asrs r4, r4, #2
  538. 2da: 42a6 cmp r6, r4
  539. 2dc: d105 bne.n 2ea <__libc_init_array+0x2e>
  540. 2de: bd70 pop {r4, r5, r6, pc}
  541. 2e0: 00b3 lsls r3, r6, #2
  542. 2e2: 58eb ldr r3, [r5, r3]
  543. 2e4: 4798 blx r3
  544. 2e6: 3601 adds r6, #1
  545. 2e8: e7ee b.n 2c8 <__libc_init_array+0xc>
  546. 2ea: 00b3 lsls r3, r6, #2
  547. 2ec: 58eb ldr r3, [r5, r3]
  548. 2ee: 4798 blx r3
  549. 2f0: 3601 adds r6, #1
  550. 2f2: e7f2 b.n 2da <__libc_init_array+0x1e>
  551. 2f4: 00000310 .word 0x00000310
  552. 2f8: 00000310 .word 0x00000310
  553. 2fc: 00000310 .word 0x00000310
  554. 300: 00000314 .word 0x00000314
  555.  
  556. 00000304 <_init>:
  557. 304: b5f8 push {r3, r4, r5, r6, r7, lr}
  558. 306: 46c0 nop ; (mov r8, r8)
  559. 308: bcf8 pop {r3, r4, r5, r6, r7}
  560. 30a: bc08 pop {r3}
  561. 30c: 469e mov lr, r3
  562. 30e: 4770 bx lr
  563.  
  564. 00000310 <__init_array_start>:
  565. 310: 000000dd .word 0x000000dd
  566.  
  567. 00000314 <_fini>:
  568. 314: b5f8 push {r3, r4, r5, r6, r7, lr}
  569. 316: 46c0 nop ; (mov r8, r8)
  570. 318: bcf8 pop {r3, r4, r5, r6, r7}
  571. 31a: bc08 pop {r3}
  572. 31c: 469e mov lr, r3
  573. 31e: 4770 bx lr
  574.  
  575. 00000320 <__fini_array_start>:
  576. 320: 000000b5 .word 0x000000b5
  577.  
  578.  
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