library IEEE;
use IEEE.std_logic_1164.all;
entity sum_8bit_ver2 is
port (
	a : in std_logic_vector(7 downto 0); -- wejscie 1
	b : in std_logic_vector(7 downto 0); -- wejscie 2
	q : out std_logic_vector(8 downto 0) -- wyjscie (suma)
	);
end sum_8bit_ver2;

architecture sum_8bit_v2 of sum_8bit_ver2 is
component half_sum is
port(
	a, b : in std_logic; -- wejscia
	sum : out std_logic; -- suma
	carry : out std_logic -- przeniesienie
	);
end component;
component sum is
port(
	a, b, ci : in std_logic; -- wejscia
	sum : out std_logic; -- suma
	co : out std_logic -- przeniesienie
	);
end component;
signal c : std_logic_vector(7 downto 0);
begin
	blok1: half_sum port map (a=>a(0), b=>b(0), sum=>q(0), carry=>c(0));
	blok2: sum port map (a=>a(1), b=>b(1), ci=>c(0), sum=>q(1), co=>c(1));
	blok3: sum port map (a=>a(2), b=>b(2), ci=>c(1), sum=>q(2), co=>c(2));
	blok4: sum port map (a=>a(3), b=>b(3), ci=>c(2), sum=>q(3), co=>c(3));
	blok5: sum port map (a=>a(4), b=>b(4), ci=>c(3), sum=>q(4), co=>c(4));
	blok6: sum port map (a=>a(5), b=>b(5), ci=>c(4), sum=>q(5), co=>c(5));
	blok7: sum port map (a=>a(6), b=>b(6), ci=>c(5), sum=>q(6), co=>c(6));
	blok8: sum port map (a=>a(7), b=>b(7), ci=>c(6), sum=>q(7), co=>q(8));
end sum_8bit_v2;