N64 Gameboy Game Link Cable

Jul 31st, 2020 (edited)
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  1. N64 Gameboy Game Link Cable
  3. This was an unreleased piece of hardware that connected an N64 controller port to a Gameboy link port.
  4. Two pieces of software--64DD titles Mario Artist: Paint Studio and Mario Artist: Communications Kit--contains fully-functional code to connect the link cable to a Pocket Printer or equally unreleased Color Pocket Printer. It is very likely specialized for use with the printers and therefore write-only, and it has nothing to do with Marigal's GB link cable that fed into the cartridge slot.
  6. The device responds to four serial port commands: reset, status requests, and mirrors of the "controller port" read/write commands.
  7. 01 03 FF device reset; returns same values as status (cmd 0)
  8. 01 03 00 status
  9. 2 device type (LE)
  10. 1 controller slot state
  11. 01 filled
  12. 02 empty
  13. 04 address CRC error
  14. 80 eeprom busy
  16. 03 21 13 read GB link cable
  17. send:
  18. 2 address & crc
  19. receive:
  20. 20 data
  21. 1 data crc
  23. 23 01 14 write GB link cable
  24. send:
  25. 2 address & crc
  26. 20 data
  27. receive:
  28. 1 data crc
  30. The device type returned by a status request is 0300, making it the only one that does not return a single bitflag.
  31. Since device types returned by status requests are little-endian, the result should read:
  32. 010300 0003 ??
  33. The ?? is presumed 01 at this point (slot filled), though it is not checked in the only software known to use it.
  35. Communication is done like any other "controller slot" device.
  37. Four address ranges are defined:
  38. 8000 power / init; device ID value is 0x83
  39. C000 control registers; 3 bytes
  40. 0x0 flags
  41. 80 GB mode; serial transfer control reg does not set the 02 "fast" flag.
  42. 40 set when writing to port as master
  43. 02 set when transfer complete; an inverted version of the serial transfer control reg 0x80 flag.
  44. 0x1 actual length of data written to port, max 32
  45. 0x2 clock / divider
  46. Delay or divider defining clock rate. B/W GB uses 0x28; when not reading status color uses 0x12.
  47. E000 write buffer; 32 bytes
  48. F000 read buffer; 32 bytes
  51. The device is initialized by writing a block of 32 bytes set to 0x83 to address 0x8000. This only needs to be done once.
  53. To send data, write the control values to the control register at address 0xC000, including the length of data in the 0x20 packet. Typical settings for GB would be "C0 xx 28", "40 xx 12" for GBC.
  54. Write the data to be sent to address 0xE000. The transfer immediately begins with N64 as master.
  55. To know when the transfer is complete, read the control register at address 0xC000. The 02 flag will be set when the transfer is complete.
  56. The port is bi-directional, so every bit sent will fill a corresponding bit in the read buffer at 0xF000.
  58. Data can only be transfered up to 32 bytes at a time. Longer packets must be broken into 32 byte clumps. (A different hardware implementation could raise this limit to 255 bytes.)
  60. Reading data from the port as a slave was not implemented in the only software known to use this device. That can be left to the hardware implementor, with some suggestion below.
  63. GB Transfers:
  64. There's very thorough documentation elsewhere on how link cables function and you would do best to refer to it. What's below was stolen from pandocs (probably).
  65. To simplify, game link cables are a twisted wire that pushes the left-most bit of the byte being transfered out, shifts the value left, then ORs the incoming value to the rightmost bit. The master device--the one that started the transfer--controls the clock.
  66. _
  67. / | CLK 5 6 GND
  68. | | S_IN 3 4 CPU_PIN_14
  69. \_| VCC +5v 1 2 S_OUT
  71. The clock is high until pulsed low, at which point a bit goes in and out. After going low eight times, the transfer is complete. The 0x80 flag in the serial transfer control reg is unset and a serial interrupt is called.
  72. The "correct" transfer speeds are based on the GB clock rates. Color units have an additional flag for running in "fast" mode, on top of double CPU speed mode.
  73. ALL 8192Hz - 1KB/s - Bit 1 cleared, Normal
  74. CGB 16384Hz - 2KB/s - Bit 1 cleared, Double Speed Mode
  75. CGB 262144Hz - 32KB/s - Bit 1 set, Normal
  76. CGB 524288Hz - 64KB/s - Bit 1 set, Double Speed Mode
  77. That said, the clock doesn't need to be regular. It can be as slow as you want, and even old DMG units have been confirmed to work at as much as 500KHz.
  78. However, the only known software that uses this cable connects to a GB Printer, and that has a timeout if data isn't received within 100ms.
  81. Considering software timeouts:
  82. Since the N64's SI could be busy or the transfer fail due to a timeout, it is suggested to attempt to resend data numerous times before confirming an error.
  83. It is suggested to attempt resending control register writes up to 10 times before assuming a timeout.
  84. Filling the write buffer should be reattempted up to 5 times.
  85. Time for transfer is directly related to the clock speed. At "normal speed", the working implementation ran its test loop about 5 times per byte sent, retesting control register reads up to 10 times per loop.
  88. Potential Implementation:
  89. The device could be implemented using an internal counter for the current byte going out. By walking left to right, blocks for data transfers greater than 32 bytes could be appended to the buffer without affecting the transfer state. Transfers complete when the index matches the length in the control register.
  90. The device should work independently and handle the transfer itself, relying on software to poll periodicly to detect if a transfer occurred.
  92. The cable was designed specifically for accessing the printers, literally called a "printer connection cable", but there's no reason it can't be utilized bidirectionally for, say, connecting GB emulators on N64 to handhelds, Super Gameboys, etc.
  93. For lack of a reference on how slaving the N64 (writing to it) may have been handled, here's a proposal!
  94. Writes operation should require the control register bit be set in order to occur. This way the buffer can be filled with outgoing data.
  95. GB transfers to slave devices are controlled only by the master device's clock signals and will occur regardless. The only indicator is the clock went low.
  96. When a transfer starts, control register 0 (flags) should be set to 0x20 to indicate a read operation is ongoing. Mask away 0x80, 0x40, 2, and 1. If the "read" flag is not set, control register 1 (length) is reset to zero.
  97. Bytes are written to the read buffer at address 0xF000, and whatever data is in the write buffer at address 0xE000 goes out. At the completion of each byte transfer, set the 01 flag in control register 0 and increment the length by 1. The user will then know data is waiting to be read and how much there is. It would be up to the user to clear the control register flags.
  99. -Zoinkity
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