CountTimeFSM

module countFSM(input logic reset, input logic inp, input logic clk, output logic [31:0] result);
typedef enum logic [1:0] {S0, S1, S2} statetype;
statetype state, newstate;
logic [31:0] temp = 0;
always_ff @(posedge clk, posedge reset)
if(reset) state <= S0;
else state <= newstate;

always_comb
    case(state)
S0:
    if(inp) newstate = S1;
    else newstate = S0;
S1:
    if(inp) newstate = S1;
    else newstate = S2;
S2:
    newstate = S0;
endcase
always_ff @(posedge clk)
case(state)
S0: temp = 0;
S1: temp = temp + 1;
S2: result = temp;
endcase
endmodule