module cau3_1_tb();
wire [6:0] out  ;
reg clk         ;
reg rst_n       ;
//
cau3_1 inst
    (
        .out    (out),
        .clk    (clk)       ,
        .rst_n  (rst_n)
    );
//init
initial begin
    clk = 1;
    rst_n = 0;
    #3 rst_n = 1;
end
//generate clk
always begin
 #1 clk = ~clk;
end
endmodule