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1
val disassembly : X86Instruction array =
2
  [|{Opcode = XOR;
3
     Address = 4096UL;
4
     Assembly = [|48uy; 49uy|];
5
     Mnemonic = "xor";
6
     Operands = "byte ptr [ecx], dh";
7
     Details =
8
      Some
9
        {ImplicitReads = [||];
10
         ImplicitWrites = [|EFLAGS|];
11
         Groups = [||];
12
         ArchitectureSpecificDetails =
13
          X86Info
14
            {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
15
             SegmentOverride = None;
16
             Opcode = [|48uy; 0uy; 0uy|];
17
             ModRM = 49uy;
18
             Operands =
19
              [|Memory ({SIB = {Scale = 1;
20
                                Index = None;
21
                                Base = ECX;};
22-
                         Displacement = 0L;},1uy,4uy); Register (DH,1uy)|];};};};
22+
                         Displacement = 0L;},DWord,DWord); Register (DH,Byte)|];};};};
23
    {Opcode = XOR;
24
     Address = 4098UL;
25
     Assembly = [|50uy; 51uy|];
26
     Mnemonic = "xor";
27
     Operands = "dh, byte ptr [ebx]";
28
     Details =
29
      Some
30
        {ImplicitReads = [||];
31
         ImplicitWrites = [|EFLAGS|];
32
         Groups = [||];
33
         ArchitectureSpecificDetails =
34
          X86Info
35
            {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
36
             SegmentOverride = None;
37
             Opcode = [|50uy; 0uy; 0uy|];
38
             ModRM = 51uy;
39
             Operands =
40-
              [|Register (DH,1uy); Memory ({SIB = {Scale = 1;
40+
              [|Register (DH,Byte); Memory ({SIB = {Scale = 1;
41-
                                                   Index = None;
41+
                                                    Index = None;
42-
                                                   Base = EBX;};
42+
                                                    Base = EBX;};
43-
                                            Displacement = 0L;},1uy,4uy)|];};};};
43+
                                             Displacement = 0L;},DWord,DWord)|];};};};
44
    {Opcode = XOR;
45
     Address = 4100UL;
46
     Assembly = [|52uy; 53uy|];
47
     Mnemonic = "xor";
48
     Operands = "al, 0x35";
49
     Details =
50
      Some
51
        {ImplicitReads = [||];
52
         ImplicitWrites = [|EFLAGS|];
53
         Groups = [||];
54
         ArchitectureSpecificDetails =
55
          X86Info {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
56
                   SegmentOverride = None;
57
                   Opcode = [|52uy; 0uy; 0uy|];
58
                   ModRM = 0uy;
59-
                   Operands = [|Register (AL,4uy); Immediate (53L,1uy)|];};};};
59+
                   Operands = [|Register (AL,DWord); Immediate (53L,Byte)|];};};};
60
    {Opcode = AAA;
61
     Address = 4102UL;
62
     Assembly = [|54uy; 55uy|];
63
     Mnemonic = "aaa";
64
     Operands = "";
65
     Details =
66
      Some
67
        {ImplicitReads = [||];
68
         ImplicitWrites = [||];
69
         Groups = [|NOT64BITMODE|];
70
         ArchitectureSpecificDetails =
71
          X86Info {Prefix = [|1uy; 0uy; 0uy; 0uy; 0uy|];
72
                   SegmentOverride = SS;
73
                   Opcode = [|55uy; 0uy; 0uy|];
74
                   ModRM = 0uy;
75
                   Operands = [||];};};};
76
    {Opcode = CMP;
77
     Address = 4104UL;
78
     Assembly = [|56uy; 57uy|];
79
     Mnemonic = "cmp";
80
     Operands = "byte ptr [ecx], bh";
81
     Details =
82
      Some
83
        {ImplicitReads = [||];
84
         ImplicitWrites = [|EFLAGS|];
85
         Groups = [||];
86
         ArchitectureSpecificDetails =
87
          X86Info
88
            {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
89
             SegmentOverride = None;
90
             Opcode = [|56uy; 0uy; 0uy|];
91
             ModRM = 57uy;
92
             Operands =
93
              [|Memory ({SIB = {Scale = 1;
94
                                Index = None;
95
                                Base = ECX;};
96-
                         Displacement = 0L;},1uy,4uy); Register (BH,1uy)|];};};};
96+
                         Displacement = 0L;},DWord,DWord); Register (BH,Byte)|];};};};
97
    {Opcode = XOR;
98
     Address = 4106UL;
99
     Assembly = [|48uy; 49uy|];
100
     Mnemonic = "xor";
101
     Operands = "byte ptr [ecx], dh";
102
     Details =
103
      Some
104
        {ImplicitReads = [||];
105
         ImplicitWrites = [|EFLAGS|];
106
         Groups = [||];
107
         ArchitectureSpecificDetails =
108
          X86Info
109
            {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
110
             SegmentOverride = None;
111
             Opcode = [|48uy; 0uy; 0uy|];
112
             ModRM = 49uy;
113
             Operands =
114
              [|Memory ({SIB = {Scale = 1;
115
                                Index = None;
116
                                Base = ECX;};
117-
                         Displacement = 0L;},1uy,4uy); Register (DH,1uy)|];};};};
117+
                         Displacement = 0L;},DWord,DWord); Register (DH,Byte)|];};};};
118
    {Opcode = XOR;
119
     Address = 4108UL;
120
     Assembly = [|50uy; 51uy|];
121
     Mnemonic = "xor";
122
     Operands = "dh, byte ptr [ebx]";
123
     Details =
124
      Some
125
        {ImplicitReads = [||];
126
         ImplicitWrites = [|EFLAGS|];
127
         Groups = [||];
128
         ArchitectureSpecificDetails =
129
          X86Info
130
            {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
131
             SegmentOverride = None;
132
             Opcode = [|50uy; 0uy; 0uy|];
133
             ModRM = 51uy;
134
             Operands =
135-
              [|Register (DH,1uy); Memory ({SIB = {Scale = 1;
135+
              [|Register (DH,Byte); Memory ({SIB = {Scale = 1;
136-
                                                   Index = None;
136+
                                                    Index = None;
137-
                                                   Base = EBX;};
137+
                                                    Base = EBX;};
138-
                                            Displacement = 0L;},1uy,4uy)|];};};};
138+
                                             Displacement = 0L;},DWord,DWord)|];};};};
139
    {Opcode = XOR;
140
     Address = 4110UL;
141
     Assembly = [|52uy; 53uy|];
142
     Mnemonic = "xor";
143
     Operands = "al, 0x35";
144
     Details =
145
      Some
146
        {ImplicitReads = [||];
147
         ImplicitWrites = [|EFLAGS|];
148
         Groups = [||];
149
         ArchitectureSpecificDetails =
150
          X86Info {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
151
                   SegmentOverride = None;
152
                   Opcode = [|52uy; 0uy; 0uy|];
153
                   ModRM = 0uy;
154-
                   Operands = [|Register (AL,4uy); Immediate (53L,1uy)|];};};};
154+
                   Operands = [|Register (AL,DWord); Immediate (53L,Byte)|];};};};
155
    {Opcode = AAA;
156
     Address = 4112UL;
157
     Assembly = [|54uy; 55uy|];
158
     Mnemonic = "aaa";
159
     Operands = "";
160
     Details =
161
      Some
162
        {ImplicitReads = [||];
163
         ImplicitWrites = [||];
164
         Groups = [|NOT64BITMODE|];
165
         ArchitectureSpecificDetails =
166
          X86Info {Prefix = [|1uy; 0uy; 0uy; 0uy; 0uy|];
167
                   SegmentOverride = SS;
168
                   Opcode = [|55uy; 0uy; 0uy|];
169
                   ModRM = 0uy;
170
                   Operands = [||];};};};
171
    {Opcode = CMP;
172
     Address = 4114UL;
173
     Assembly = [|56uy; 57uy|];
174
     Mnemonic = "cmp";
175
     Operands = "byte ptr [ecx], bh";
176
     Details =
177
      Some
178
        {ImplicitReads = [||];
179
         ImplicitWrites = [|EFLAGS|];
180
         Groups = [||];
181
         ArchitectureSpecificDetails =
182
          X86Info
183
            {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
184
             SegmentOverride = None;
185
             Opcode = [|56uy; 0uy; 0uy|];
186
             ModRM = 57uy;
187
             Operands =
188
              [|Memory ({SIB = {Scale = 1;
189
                                Index = None;
190
                                Base = ECX;};
191-
                         Displacement = 0L;},1uy,4uy); Register (BH,1uy)|];};};};
191+
                         Displacement = 0L;},DWord,DWord); Register (BH,Byte)|];};};};
192
    {Opcode = FDIVR;
193
     Address = 4116UL;
194
     Assembly = [|216uy; 191uy; 255uy; 255uy; 159uy; 133uy|];
195
     Mnemonic = "fdivr";
196
     Operands = "dword ptr [edi + 0x859fffff]";
197
     Details =
198
      Some
199
        {ImplicitReads = [||];
200
         ImplicitWrites = [|FPSW|];
201
         Groups = [||];
202
         ArchitectureSpecificDetails =
203
          X86Info
204
            {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
205
             SegmentOverride = None;
206
             Opcode = [|216uy; 0uy; 0uy|];
207
             ModRM = 191uy;
208-
             Operands = [|Memory ({SIB = {Scale = 1;
208+
209-
                                          Index = None;

209+
210-
                                          Base = EDI;};

210+
211-
                                   Displacement = -2053111809L;},4uy,4uy)|];};};};

211+
                                Base = EDI;};

212
                         Displacement = -2053111809L;},DWord,DWord)|];};};};

213
    {Opcode = ADD;

214
     Address = 4122UL;

215
     Assembly = [|4uy; 8uy|];

216
     Mnemonic = "add";

217
     Operands = "al, 8";

218
     Details =

219
      Some

220
        {ImplicitReads = [||];

221
         ImplicitWrites = [|EFLAGS|];

222
         Groups = [||];

223
         ArchitectureSpecificDetails =

224
          X86Info {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];

225
                   SegmentOverride = None;

226
                   Opcode = [|4uy; 0uy; 0uy|];

227-
                   Operands = [|Register (AL,4uy); Immediate (8L,1uy)|];};};};

227+
228
                   Operands = [|Register (AL,DWord); Immediate (8L,Byte)|];};};};

229
    {Opcode = MOV;

230
     Address = 4124UL;

231
     Assembly = [|176uy; 134uy|];

232
     Mnemonic = "mov";

233
     Operands = "al, -0x7a";

234
     Details =

235
      Some

236
        {ImplicitReads = [||];

237
         ImplicitWrites = [||];

238
         Groups = [||];

239
         ArchitectureSpecificDetails =

240
          X86Info {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];

241
                   SegmentOverride = None;

242
                   Opcode = [|176uy; 0uy; 0uy|];

243-
                   Operands = [|Register (AL,1uy); Immediate (-122L,1uy)|];};};};

243+
244
                   Operands = [|Register (AL,Byte); Immediate (-122L,Byte)|];};};};

245
    {Opcode = ADD;

246
     Address = 4126UL;

247
     Assembly = [|4uy; 8uy|];

248
     Mnemonic = "add";

249
     Operands = "al, 8";

250
     Details =

251
      Some

252
        {ImplicitReads = [||];

253
         ImplicitWrites = [|EFLAGS|];

254
         Groups = [||];

255
         ArchitectureSpecificDetails =

256
          X86Info {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];

257
                   SegmentOverride = None;

258
                   Opcode = [|4uy; 0uy; 0uy|];

259-
                   Operands = [|Register (AL,4uy); Immediate (8L,1uy)|];};};};

259+
260
                   Operands = [|Register (AL,DWord); Immediate (8L,Byte)|];};};};

261
    {Opcode = XOR;

262
     Address = 4128UL;

263
     Assembly = [|48uy; 49uy|];

264
     Mnemonic = "xor";

265
     Operands = "byte ptr [ecx], dh";

266
     Details =

267
      Some

268
        {ImplicitReads = [||];

269
         ImplicitWrites = [|EFLAGS|];

270
         Groups = [||];

271
         ArchitectureSpecificDetails =

272
          X86Info

273
            {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];

274
             SegmentOverride = None;

275
             Opcode = [|48uy; 0uy; 0uy|];

276
             ModRM = 49uy;

277
             Operands =

278
              [|Memory ({SIB = {Scale = 1;

279
                                Index = None;

280-
                         Displacement = 0L;},1uy,4uy); Register (DH,1uy)|];};};};

280+
281
                         Displacement = 0L;},DWord,DWord); Register (DH,Byte)|];};};};

282
    {Opcode = XOR;

283
     Address = 4130UL;

284
     Assembly = [|50uy; 51uy|];

285
     Mnemonic = "xor";

286
     Operands = "dh, byte ptr [ebx]";

287
     Details =

288
      Some

289
        {ImplicitReads = [||];

290
         ImplicitWrites = [|EFLAGS|];

291
         Groups = [||];

292
         ArchitectureSpecificDetails =

293
          X86Info

294
            {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];

295
             SegmentOverride = None;

296
             Opcode = [|50uy; 0uy; 0uy|];

297
             ModRM = 51uy;

298-
              [|Register (DH,1uy); Memory ({SIB = {Scale = 1;

298+
299-
                                                   Index = None;

299+
              [|Register (DH,Byte); Memory ({SIB = {Scale = 1;

300-
                                                   Base = EBX;};

300+
                                                    Index = None;

301-
                                            Displacement = 0L;},1uy,4uy)|];};};};

301+
                                                    Base = EBX;};

302
                                             Displacement = 0L;},DWord,DWord)|];};};};

303
    {Opcode = XOR;

304
     Address = 4132UL;

305
     Assembly = [|48uy; 49uy|];

306
     Mnemonic = "xor";

307
     Operands = "byte ptr [ecx], dh";

308
     Details =

309
      Some

310
        {ImplicitReads = [||];

311
         ImplicitWrites = [|EFLAGS|];

312
         Groups = [||];

313
         ArchitectureSpecificDetails =

314
          X86Info

315
            {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];

316
             SegmentOverride = None;

317
             Opcode = [|48uy; 0uy; 0uy|];

318
             ModRM = 49uy;

319
             Operands =

320
              [|Memory ({SIB = {Scale = 1;

321
                                Index = None;

322-
                         Displacement = 0L;},1uy,4uy); Register (DH,1uy)|];};};};

322+
323
                         Displacement = 0L;},DWord,DWord); Register (DH,Byte)|];};};};

324
    {Opcode = XOR;

325
     Address = 4134UL;

326
     Assembly = [|50uy; 51uy|];

327
     Mnemonic = "xor";

328
     Operands = "dh, byte ptr [ebx]";

329
     Details =

330
      Some

331
        {ImplicitReads = [||];

332
         ImplicitWrites = [|EFLAGS|];

333
         Groups = [||];

334
         ArchitectureSpecificDetails =

335
          X86Info

336
            {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];

337
             SegmentOverride = None;

338
             Opcode = [|50uy; 0uy; 0uy|];

339
             ModRM = 51uy;

340-
              [|Register (DH,1uy); Memory ({SIB = {Scale = 1;

340+
341-
                                                   Index = None;

341+
              [|Register (DH,Byte); Memory ({SIB = {Scale = 1;

342-
                                                   Base = EBX;};

342+
                                                    Index = None;

343-
                                            Displacement = 0L;},1uy,4uy)|];};};};

343+
                                                    Base = EBX;};

344
                                             Displacement = 0L;},DWord,DWord)|];};};};

345
    {Opcode = XOR;

346
     Address = 4136UL;

347
     Assembly = [|52uy; 53uy|];

348
     Mnemonic = "xor";

349
     Operands = "al, 0x35";

350
     Details =

351
      Some

352
        {ImplicitReads = [||];

353
         ImplicitWrites = [|EFLAGS|];

354
         Groups = [||];

355
         ArchitectureSpecificDetails =

356
          X86Info {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];

357
                   SegmentOverride = None;

358
                   Opcode = [|52uy; 0uy; 0uy|];

359-
                   Operands = [|Register (AL,4uy); Immediate (53L,1uy)|];};};};

359+
360
                   Operands = [|Register (AL,DWord); Immediate (53L,Byte)|];};};};

361
    {Opcode = AAA;

362
     Address = 4138UL;

363
     Assembly = [|54uy; 55uy|];

364
     Mnemonic = "aaa";

365
     Operands = "";

366
     Details =

367
      Some

368
        {ImplicitReads = [||];

369
         ImplicitWrites = [||];

370
         Groups = [|NOT64BITMODE|];

371
         ArchitectureSpecificDetails =

372
          X86Info {Prefix = [|1uy; 0uy; 0uy; 0uy; 0uy|];

373
                   SegmentOverride = SS;

374
                   Opcode = [|55uy; 0uy; 0uy|];

375
                   ModRM = 0uy;

376
                   Operands = [||];};};}|]
        

    


            


                                


        

            



                
    

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