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AngraMainyu

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AngraMainyu
Jul 6th, 2014
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  1. val disassembly : X86Instruction array =
  2.   [|{Opcode = XOR;
  3.      Address = 4096UL;
  4.      Assembly = [|48uy; 49uy|];
  5.      Mnemonic = "xor";
  6.      Operands = "byte ptr [ecx], dh";
  7.      Details =
  8.       Some
  9.         {ImplicitReads = [||];
  10.          ImplicitWrites = [|EFLAGS|];
  11.          Groups = [||];
  12.          ArchitectureSpecificDetails =
  13.           X86Info
  14.             {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
  15.              SegmentOverride = None;
  16.              Opcode = [|48uy; 0uy; 0uy|];
  17.              ModRM = 49uy;
  18.              Operands =
  19.               [|Memory ({SIB = {Scale = 1;
  20.                                 Index = None;
  21.                                 Base = ECX;};
  22.                          Displacement = 0L;},1uy,4uy); Register (DH,1uy)|];};};};
  23.     {Opcode = XOR;
  24.      Address = 4098UL;
  25.      Assembly = [|50uy; 51uy|];
  26.      Mnemonic = "xor";
  27.      Operands = "dh, byte ptr [ebx]";
  28.      Details =
  29.       Some
  30.         {ImplicitReads = [||];
  31.          ImplicitWrites = [|EFLAGS|];
  32.          Groups = [||];
  33.          ArchitectureSpecificDetails =
  34.           X86Info
  35.             {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
  36.              SegmentOverride = None;
  37.              Opcode = [|50uy; 0uy; 0uy|];
  38.              ModRM = 51uy;
  39.              Operands =
  40.               [|Register (DH,1uy); Memory ({SIB = {Scale = 1;
  41.                                                    Index = None;
  42.                                                    Base = EBX;};
  43.                                             Displacement = 0L;},1uy,4uy)|];};};};
  44.     {Opcode = XOR;
  45.      Address = 4100UL;
  46.      Assembly = [|52uy; 53uy|];
  47.      Mnemonic = "xor";
  48.      Operands = "al, 0x35";
  49.      Details =
  50.       Some
  51.         {ImplicitReads = [||];
  52.          ImplicitWrites = [|EFLAGS|];
  53.          Groups = [||];
  54.          ArchitectureSpecificDetails =
  55.           X86Info {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
  56.                    SegmentOverride = None;
  57.                    Opcode = [|52uy; 0uy; 0uy|];
  58.                    ModRM = 0uy;
  59.                    Operands = [|Register (AL,4uy); Immediate (53L,1uy)|];};};};
  60.     {Opcode = AAA;
  61.      Address = 4102UL;
  62.      Assembly = [|54uy; 55uy|];
  63.      Mnemonic = "aaa";
  64.      Operands = "";
  65.      Details =
  66.       Some
  67.         {ImplicitReads = [||];
  68.          ImplicitWrites = [||];
  69.          Groups = [|NOT64BITMODE|];
  70.          ArchitectureSpecificDetails =
  71.           X86Info {Prefix = [|1uy; 0uy; 0uy; 0uy; 0uy|];
  72.                    SegmentOverride = SS;
  73.                    Opcode = [|55uy; 0uy; 0uy|];
  74.                    ModRM = 0uy;
  75.                    Operands = [||];};};};
  76.     {Opcode = CMP;
  77.      Address = 4104UL;
  78.      Assembly = [|56uy; 57uy|];
  79.      Mnemonic = "cmp";
  80.      Operands = "byte ptr [ecx], bh";
  81.      Details =
  82.       Some
  83.         {ImplicitReads = [||];
  84.          ImplicitWrites = [|EFLAGS|];
  85.          Groups = [||];
  86.          ArchitectureSpecificDetails =
  87.           X86Info
  88.             {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
  89.              SegmentOverride = None;
  90.              Opcode = [|56uy; 0uy; 0uy|];
  91.              ModRM = 57uy;
  92.              Operands =
  93.               [|Memory ({SIB = {Scale = 1;
  94.                                 Index = None;
  95.                                 Base = ECX;};
  96.                          Displacement = 0L;},1uy,4uy); Register (BH,1uy)|];};};};
  97.     {Opcode = XOR;
  98.      Address = 4106UL;
  99.      Assembly = [|48uy; 49uy|];
  100.      Mnemonic = "xor";
  101.      Operands = "byte ptr [ecx], dh";
  102.      Details =
  103.       Some
  104.         {ImplicitReads = [||];
  105.          ImplicitWrites = [|EFLAGS|];
  106.          Groups = [||];
  107.          ArchitectureSpecificDetails =
  108.           X86Info
  109.             {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
  110.              SegmentOverride = None;
  111.              Opcode = [|48uy; 0uy; 0uy|];
  112.              ModRM = 49uy;
  113.              Operands =
  114.               [|Memory ({SIB = {Scale = 1;
  115.                                 Index = None;
  116.                                 Base = ECX;};
  117.                          Displacement = 0L;},1uy,4uy); Register (DH,1uy)|];};};};
  118.     {Opcode = XOR;
  119.      Address = 4108UL;
  120.      Assembly = [|50uy; 51uy|];
  121.      Mnemonic = "xor";
  122.      Operands = "dh, byte ptr [ebx]";
  123.      Details =
  124.       Some
  125.         {ImplicitReads = [||];
  126.          ImplicitWrites = [|EFLAGS|];
  127.          Groups = [||];
  128.          ArchitectureSpecificDetails =
  129.           X86Info
  130.             {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
  131.              SegmentOverride = None;
  132.              Opcode = [|50uy; 0uy; 0uy|];
  133.              ModRM = 51uy;
  134.              Operands =
  135.               [|Register (DH,1uy); Memory ({SIB = {Scale = 1;
  136.                                                    Index = None;
  137.                                                    Base = EBX;};
  138.                                             Displacement = 0L;},1uy,4uy)|];};};};
  139.     {Opcode = XOR;
  140.      Address = 4110UL;
  141.      Assembly = [|52uy; 53uy|];
  142.      Mnemonic = "xor";
  143.      Operands = "al, 0x35";
  144.      Details =
  145.       Some
  146.         {ImplicitReads = [||];
  147.          ImplicitWrites = [|EFLAGS|];
  148.          Groups = [||];
  149.          ArchitectureSpecificDetails =
  150.           X86Info {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
  151.                    SegmentOverride = None;
  152.                    Opcode = [|52uy; 0uy; 0uy|];
  153.                    ModRM = 0uy;
  154.                    Operands = [|Register (AL,4uy); Immediate (53L,1uy)|];};};};
  155.     {Opcode = AAA;
  156.      Address = 4112UL;
  157.      Assembly = [|54uy; 55uy|];
  158.      Mnemonic = "aaa";
  159.      Operands = "";
  160.      Details =
  161.       Some
  162.         {ImplicitReads = [||];
  163.          ImplicitWrites = [||];
  164.          Groups = [|NOT64BITMODE|];
  165.          ArchitectureSpecificDetails =
  166.           X86Info {Prefix = [|1uy; 0uy; 0uy; 0uy; 0uy|];
  167.                    SegmentOverride = SS;
  168.                    Opcode = [|55uy; 0uy; 0uy|];
  169.                    ModRM = 0uy;
  170.                    Operands = [||];};};};
  171.     {Opcode = CMP;
  172.      Address = 4114UL;
  173.      Assembly = [|56uy; 57uy|];
  174.      Mnemonic = "cmp";
  175.      Operands = "byte ptr [ecx], bh";
  176.      Details =
  177.       Some
  178.         {ImplicitReads = [||];
  179.          ImplicitWrites = [|EFLAGS|];
  180.          Groups = [||];
  181.          ArchitectureSpecificDetails =
  182.           X86Info
  183.             {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
  184.              SegmentOverride = None;
  185.              Opcode = [|56uy; 0uy; 0uy|];
  186.              ModRM = 57uy;
  187.              Operands =
  188.               [|Memory ({SIB = {Scale = 1;
  189.                                 Index = None;
  190.                                 Base = ECX;};
  191.                          Displacement = 0L;},1uy,4uy); Register (BH,1uy)|];};};};
  192.     {Opcode = FDIVR;
  193.      Address = 4116UL;
  194.      Assembly = [|216uy; 191uy; 255uy; 255uy; 159uy; 133uy|];
  195.      Mnemonic = "fdivr";
  196.      Operands = "dword ptr [edi + 0x859fffff]";
  197.      Details =
  198.       Some
  199.         {ImplicitReads = [||];
  200.          ImplicitWrites = [|FPSW|];
  201.          Groups = [||];
  202.          ArchitectureSpecificDetails =
  203.           X86Info
  204.             {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
  205.              SegmentOverride = None;
  206.              Opcode = [|216uy; 0uy; 0uy|];
  207.              ModRM = 191uy;
  208.              Operands = [|Memory ({SIB = {Scale = 1;
  209.                                           Index = None;
  210.                                           Base = EDI;};
  211.                                    Displacement = -2053111809L;},4uy,4uy)|];};};};
  212.     {Opcode = ADD;
  213.      Address = 4122UL;
  214.      Assembly = [|4uy; 8uy|];
  215.      Mnemonic = "add";
  216.      Operands = "al, 8";
  217.      Details =
  218.       Some
  219.         {ImplicitReads = [||];
  220.          ImplicitWrites = [|EFLAGS|];
  221.          Groups = [||];
  222.          ArchitectureSpecificDetails =
  223.           X86Info {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
  224.                    SegmentOverride = None;
  225.                    Opcode = [|4uy; 0uy; 0uy|];
  226.                    ModRM = 0uy;
  227.                    Operands = [|Register (AL,4uy); Immediate (8L,1uy)|];};};};
  228.     {Opcode = MOV;
  229.      Address = 4124UL;
  230.      Assembly = [|176uy; 134uy|];
  231.      Mnemonic = "mov";
  232.      Operands = "al, -0x7a";
  233.      Details =
  234.       Some
  235.         {ImplicitReads = [||];
  236.          ImplicitWrites = [||];
  237.          Groups = [||];
  238.          ArchitectureSpecificDetails =
  239.           X86Info {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
  240.                    SegmentOverride = None;
  241.                    Opcode = [|176uy; 0uy; 0uy|];
  242.                    ModRM = 0uy;
  243.                    Operands = [|Register (AL,1uy); Immediate (-122L,1uy)|];};};};
  244.     {Opcode = ADD;
  245.      Address = 4126UL;
  246.      Assembly = [|4uy; 8uy|];
  247.      Mnemonic = "add";
  248.      Operands = "al, 8";
  249.      Details =
  250.       Some
  251.         {ImplicitReads = [||];
  252.          ImplicitWrites = [|EFLAGS|];
  253.          Groups = [||];
  254.          ArchitectureSpecificDetails =
  255.           X86Info {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
  256.                    SegmentOverride = None;
  257.                    Opcode = [|4uy; 0uy; 0uy|];
  258.                    ModRM = 0uy;
  259.                    Operands = [|Register (AL,4uy); Immediate (8L,1uy)|];};};};
  260.     {Opcode = XOR;
  261.      Address = 4128UL;
  262.      Assembly = [|48uy; 49uy|];
  263.      Mnemonic = "xor";
  264.      Operands = "byte ptr [ecx], dh";
  265.      Details =
  266.       Some
  267.         {ImplicitReads = [||];
  268.          ImplicitWrites = [|EFLAGS|];
  269.          Groups = [||];
  270.          ArchitectureSpecificDetails =
  271.           X86Info
  272.             {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
  273.              SegmentOverride = None;
  274.              Opcode = [|48uy; 0uy; 0uy|];
  275.              ModRM = 49uy;
  276.              Operands =
  277.               [|Memory ({SIB = {Scale = 1;
  278.                                 Index = None;
  279.                                 Base = ECX;};
  280.                          Displacement = 0L;},1uy,4uy); Register (DH,1uy)|];};};};
  281.     {Opcode = XOR;
  282.      Address = 4130UL;
  283.      Assembly = [|50uy; 51uy|];
  284.      Mnemonic = "xor";
  285.      Operands = "dh, byte ptr [ebx]";
  286.      Details =
  287.       Some
  288.         {ImplicitReads = [||];
  289.          ImplicitWrites = [|EFLAGS|];
  290.          Groups = [||];
  291.          ArchitectureSpecificDetails =
  292.           X86Info
  293.             {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
  294.              SegmentOverride = None;
  295.              Opcode = [|50uy; 0uy; 0uy|];
  296.              ModRM = 51uy;
  297.              Operands =
  298.               [|Register (DH,1uy); Memory ({SIB = {Scale = 1;
  299.                                                    Index = None;
  300.                                                    Base = EBX;};
  301.                                             Displacement = 0L;},1uy,4uy)|];};};};
  302.     {Opcode = XOR;
  303.      Address = 4132UL;
  304.      Assembly = [|48uy; 49uy|];
  305.      Mnemonic = "xor";
  306.      Operands = "byte ptr [ecx], dh";
  307.      Details =
  308.       Some
  309.         {ImplicitReads = [||];
  310.          ImplicitWrites = [|EFLAGS|];
  311.          Groups = [||];
  312.          ArchitectureSpecificDetails =
  313.           X86Info
  314.             {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
  315.              SegmentOverride = None;
  316.              Opcode = [|48uy; 0uy; 0uy|];
  317.              ModRM = 49uy;
  318.              Operands =
  319.               [|Memory ({SIB = {Scale = 1;
  320.                                 Index = None;
  321.                                 Base = ECX;};
  322.                          Displacement = 0L;},1uy,4uy); Register (DH,1uy)|];};};};
  323.     {Opcode = XOR;
  324.      Address = 4134UL;
  325.      Assembly = [|50uy; 51uy|];
  326.      Mnemonic = "xor";
  327.      Operands = "dh, byte ptr [ebx]";
  328.      Details =
  329.       Some
  330.         {ImplicitReads = [||];
  331.          ImplicitWrites = [|EFLAGS|];
  332.          Groups = [||];
  333.          ArchitectureSpecificDetails =
  334.           X86Info
  335.             {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
  336.              SegmentOverride = None;
  337.              Opcode = [|50uy; 0uy; 0uy|];
  338.              ModRM = 51uy;
  339.              Operands =
  340.               [|Register (DH,1uy); Memory ({SIB = {Scale = 1;
  341.                                                    Index = None;
  342.                                                    Base = EBX;};
  343.                                             Displacement = 0L;},1uy,4uy)|];};};};
  344.     {Opcode = XOR;
  345.      Address = 4136UL;
  346.      Assembly = [|52uy; 53uy|];
  347.      Mnemonic = "xor";
  348.      Operands = "al, 0x35";
  349.      Details =
  350.       Some
  351.         {ImplicitReads = [||];
  352.          ImplicitWrites = [|EFLAGS|];
  353.          Groups = [||];
  354.          ArchitectureSpecificDetails =
  355.           X86Info {Prefix = [|0uy; 0uy; 0uy; 0uy; 0uy|];
  356.                    SegmentOverride = None;
  357.                    Opcode = [|52uy; 0uy; 0uy|];
  358.                    ModRM = 0uy;
  359.                    Operands = [|Register (AL,4uy); Immediate (53L,1uy)|];};};};
  360.     {Opcode = AAA;
  361.      Address = 4138UL;
  362.      Assembly = [|54uy; 55uy|];
  363.      Mnemonic = "aaa";
  364.      Operands = "";
  365.      Details =
  366.       Some
  367.         {ImplicitReads = [||];
  368.          ImplicitWrites = [||];
  369.          Groups = [|NOT64BITMODE|];
  370.          ArchitectureSpecificDetails =
  371.           X86Info {Prefix = [|1uy; 0uy; 0uy; 0uy; 0uy|];
  372.                    SegmentOverride = SS;
  373.                    Opcode = [|55uy; 0uy; 0uy|];
  374.                    ModRM = 0uy;
  375.                    Operands = [||];};};}|]
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