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| 1 | library IEEE; | |
| 2 | use IEEE.std_logic_1164.all; | |
| 3 | ||
| 4 | entity uklad is | |
| 5 | port( | |
| 6 | x: in std_logic_vector(3 downto 0); | |
| 7 | z : out std_logic | |
| 8 | ); | |
| 9 | ||
| 10 | end uklad; | |
| 11 | ||
| 12 | architecture uklad_a of uklad is | |
| 13 | begin | |
| 14 | case x is | |
| 15 | - | when "0001" to "0011" => z <= '1'; |
| 15 | + | when "0001" | "0010" | "0011" | "0110" | "0111"| "1000" | "1001"| "1010" => z <= '1'; |
| 16 | - | when "0110" to "1010" => z <= '1'; |
| 16 | + | |
| 17 | end uklad_a; |
