library IEEE;
use IEEE.std_logic_1164.all;

entity uklad is
 port(
 x: in std_logic_vector(3 downto 0);
 z : out std_logic
 );

end uklad;

architecture uklad_a of uklad is
begin
    case x is
        when "0001" | "0010" | "0011" | "0110" | "0111"| "1000" | "1001"| "1010" => z <= '1';
        when others => z <= '0';
end uklad_a;