module teljari(x,y,en,clk,reset,Q);

input x;
input en;
input y;
input clk;
input reset;
output[2:0] Q;

wire [2:0] D;

assign D[0] = !Q[0]&(!en);
assign D[1] = (((!Q[1]&!x&Q[0])|(!Q[1]&x&!Q[0])|(Q[1]&!x&!Q[0])|(Q[1]&x&Q[0]))|((Q[1]^Q[0]^x)&y))|en;
assign D[2] = (((!Q[2]&!Q[1]&x&!Q[0])|(!Q[2]&Q[1]&!x&Q[0])|(Q[2]&!x&!Q[0])|(Q[2]&Q[1]&x)|(Q[2]&!Q[1]&Q[0]))&y)^((!Q[2]&!Q[1]&x&!Q[0])|(!Q[2]&Q[1]&!x&Q[0])|(Q[2]&!x&!Q[0])|(Q[2]&Q[1]&x)|(Q[2]&!Q[1]&Q[0]))|en;

D_vippa D0(D[0],reset,clk,Q[0]);
D_vippa D1(D[1],reset,clk,Q[1]);
D_vippa D2(D[2],reset,clk,Q[2]);
endmodule