triac_test.cir

* /opt/geda/bin/gnetlist -g spice-sdb -o triac_test.cir triac_test.sch
*********************************************************
* Spice file generated by gnetlist                      *
* spice-sdb version 4.28.2007 by SDB --                 *
* provides advanced spice netlisting capability.        *
* Documentation at http://www.brorson.com/gEDA/SPICE/   *
*********************************************************
*vvvvvvvv  Included SPICE model from controller.lib vvvvvvvv
***********************************************************************
* 				DIAC PSpice Models                    *
***********************************************************************
.SUBCKT DIAC DIAC_IN DIAC_OUT
+Tr=0.342
+Vbo=13.6V
+Delta_V=19V
+Ibo=15uA
*
*Tr:      Rise time (in µs)
*Vbo:	  Break over voltage
*Delta_V: Dynamic breakover voltage
*Ibo:     Breakover current

****************
* Switch Model *
****************
* Voff=0.1V Von=0.99V
.MODEL        S_S1 SW Roff=1e7 Ron=2.2 vt=0.545v vh=0.445v


* D1,D2,S1 = Delta_V
D_D1         N06161 N01041 DZ19V
D_D2         N06161 N01060 DZ19V

* Delta_V control
S_S1         N01041 N01060 N02098 DIAC_OUT S_S1
V_IDIAC1     DIAC_IN N01041 DC 0Vdc AC 0Vac
E_ABM1       TRG DIAC_OUT vol=' ABS(I(V_IDIAC1))>{Ibo} ? 1 : 0'
R_R1         N02098 TRG r = {1.462 * Tr}
C_C1         N02098 DIAC_OUT 1u IC=0
RS_S1        N02098 DIAC_OUT 1G

* D3,D4 complete the Vbo
D_D3         N10655 N01060 DZ14V
D_D4         N10655 DIAC_OUT DZ14V

C_C2         DIAC_IN DIAC_OUT 10p
****************
* Diodes Model *
****************
.model DZ19V D(Is=6.994f Rs=5.612 Ikf=0 N=1 Eg=1.11 M=.2906
+	     Vj=.75 Fc=.5 Isr=2.088n Nr=2 Bv={Delta_V} Ibv=.17098 Nbv=1.2072
+	     Ibvl=2.002m Nbvl=1.1457 Tbv1=888.89u)
*	Vz = 18 @ 14mA, Zz = 37 @ 1mA, Zz = 11 @ 5mA, Zz = 7.9 @ 20mA
.model DZ14V  	D(Is=3.142f Rs=0.1 Ikf=0 N=1 Xti=3 Eg=1.11 M=.3282
+		Vj=.75 Fc=.5 Isr=1.973n Nr=2 Bv={Vbo-Delta_V} Ibv=.14467 Nbv=1.093
+		Ibvl=.1m Nbvl=1.2722 Tbv1=001433.3u)
*
.ends
*
*********************************************************************
* 				Standard DIACs			    *
*********************************************************************
*

.subckt DB3 DIAC_IN DIAC_OUT
X1 DIAC_IN DIAC_OUT DIAC
+Tr=0.342
+Vbo=32V
+Delta_V=5V
+Ibo=50uA
* 2008 / ST / Rev 0
.ends
*$


***********************************************************************
* 				Triacs PSpice Models                  *
***********************************************************************
* Note :
*
*	This triac model simulates:
*	-Igt (the same for all quadrants) MAX of the specification
*       -Il  (the same for all quadrants) Typ of the specification
*       -Ih  (the same for both polarity) Typ of the specification
*       -VDRM
*       -VRRM
*       -(di/dt)c and (dV/dt)c parameters are simulated only if those
*        constraints exceed very higly the specified limits.
*       -Power dissipation is realistic and correspond to a typical
*        triac
*
*       All these parameters are constant, and don't vary neither
*       with temperature nor other parameters.
*
*       The "STANDARD" parameter switch between
*       4 quadrants triacs (STANDARD = 1) and
*       3 quadrants triacs (STANDARD = 0.
*       The "STANDARD" parameter maintains or suppress the triggering
*       possibility of the triac in the fourth quadrant, and has
*       absolutely NO EFFECT on other parameters.
*
*		For a correct triac behavior, the "Maximum step size"	must be below
*       or equal 20µs.
*
*
*
*$
.subckt Triac_ST A K G
+ Vdrm=400v
+ Igt=20ma
+ Ih=6ma
+ Rt=0.01
+ Standard=1
*
* Vdrm : Repetitive forward off-state voltage
* Ih   : Holding current
* Igt  : Gate trigger current
* Rt   : Dynamic on-state resistance
* Standard : Differenciation between Snubberless and Standard Triacs
* (Standard=0 => Snubberless Triacs, Standard=1 => Standard Triacs)
*
*****************
* Power circuit *
*****************
*
****************
*Switch circuit*
****************
* Q1 & Q2 Conduction
S_S3         A Plip1 positive GND Smain
*RS_S3        positive 0 1G
D_DAK1         Plip1 Plip2 Dak
R_Rlip         Plip1 Plip2  1k
V_Viak         Plip2 K DC 0 AC 0
*
* Q3 & Q4 Conduction
S_S4         A Plin1 negative GND Smain
*RS_S4        negative 0 1G
D_DKA1         Plin2 Plin1 Dak
R_Rlin         Plin1 Plin2  1k
V_Vika         K Plin2 DC 0 AC 0
**************
*Gate circuit*
**************
R_Rgk         G K  10G
D_DGKi         Pg2 G Dgk
D_DGKd         G Pg2 Dgk
V_Vig         Pg2 K DC 0 AC 0
R_Rlig         G Pg2  1k
*******************
*Interface circuit*
*******************
* positive pilot
R_Rp         Controlp positive  2.2
C_Cp         GND positive  1u
E_IF15OR3         Controlp GND vol = ' V(CMDIG)>0.5 || V(CMDILIH)>0.5 || V(CMDVdrm)>0.5 ? 400 : 0 '
*
* negative pilot
R_Rn         Controln negative  2.2
C_Cn         GND negative  1u
E_IF14OR3         Controln GND vol = ' V(CMDIG)>0.5 || V(CMDILIHN)>0.5 || V(CMDVdrm)>0.5 ? 400 : 0 '
*
*
******************
* Pilots circuit *
******************
******************
* Pilot Gate     *
******************
E_IF1IG         inIG GND vol='( ABS(I(V_Vig)) ) > Igt  ? 1 : 0 '
E_MULT2MULT         CMDIG GND vol='V(Q4)*V(inIG)'
E_IF2Quadrant4         Q4 GND vol =
+ 'I(V_Vig)>Igt && V(A)-V(K)<0 && Standard==0 ? 0 : 1'
*
******************
* Pilot IHIL     *
******************
*
E_IF10IL         inIL GND vol=' ((I(V_Viak))>2.5*Igt) ? 1 : 0 '
E_IF5IH         inIH GND vol=' ((I(V_Viak))>(Ih/3)) ? 1 : 0 '
*
* Flip_flop IHIL
E_IF6DIHIL         SDIHIL GND vol = '(V(inIL)*V(inIH)+V(inIH)*(1-V(inIL))*(V(CMDILIH)) )>0.5 ? 1 : 0'
C_CIHIL         CMDILIH GND  1n
R_RIHIL         SDIHIL CMDILIH  1K
R_RIHIL2         CMDILIH GND  100Meg
******************
* Pilot IHILN    *
******************
*
E_IF11ILn         inILn GND vol='I(V_Vika)>2.5*Igt ? 1 : 0 '
E_IF3IHn         inIHn GND  vol='I(V_Vika)>Ih/3 ? 1 : 0 '
* Flip_flop IHILn
E_IF4DIHILN         SDIHILN GND vol = 'V(inILn)*V(inIHn)+V(inIHn)*(1-V(inILn))*V(CMDILIHN) >0.5 ? 1 : 0'
C_CIHILn         CMDILIHN GND  1n
R_RIHILn         SDIHILN CMDILIHN  1K
R_RIHILn2         CMDILIHN GND  100Meg
******************
* Pilot VDRM     *
******************
E_IF8Vdrm         inVdrm GND vol='ABS(V(A)-V(K))>(Vdrm*1.3) ? 1 : 0 '
E_IF9IHVDRM         inIhVdrm GND vol = ' I(V_Viak)>(Vdrm*1.3)/1.2meg || I(V_Vika)>(Vdrm*1.3)/1.2meg ? 1 : 0 '
* Flip_flop VDRM
E_IF7DVDRM         SDVDRM GND vol = 'V(inVdrm)+(1-V(inVdrm))*V(inIhVdrm)*V(CMDVdrm) >0.5 ? 1 : 0 '
C_CVdrm         CMDVdrm GND  1n
R_RVdrm         SDVDRM CMDVdrm  100
R_RVdrm2        CMDVdrm GND  100Meg
****************
* Switch Model *
****************
* .MODEL Smain SW Roff=1.2meg Ron={Rt} Voff=0 Von=100
.MODEL Smain SW Roff=1.2meg Ron={Rt} Vt=50v Vh=50v
****************
* Diodes Model *
****************
.MODEL  Dak D( Is=3E-12 Cjo=5pf)
.MODEL  Dgk D( Is=1E-16 Cjo=50pf Rs=5)
.ends
*
.subckt BTB16-600BW A K G
X1 A K G Triac_ST
+ Vdrm=600v
+ Igt=50ma
+ Ih=50ma
+ Rt=0.025
+ Standard=0
* 2008 / ST / Rev 1
.ends
*$


.MODEL 1N4004 D(tnom=27. is=76.9p rs=0.042 n=1.45 tt=4.32u cjo=39.8p pb=1. mj=0.333 egap=1.11 xti=3. fc=0.5 bv=400. ibv=5.u)

*^^^^^^^^  End of included SPICE model from controller.lib ^^^^^^^^
*
*==============  Begin SPICE netlist of main design ============
.INCLUDE triac_test.cmd
Rload Vline1 TRIAC_A 10
C2 0 timing 100nF
C3 0 1 100nF
R1 Vline1 1 20K
R2 timing 1 56K
XD5 timing TRIAC_G DB3
Vline Vline1 0 SIN(0v 310v 60Hz)
XTR1 TRIAC_A 0 TRIAC_G BTB16-600BW
.end