`timescale 1ns/10ps
module bit_stuffing(input logic inp_seq, bs, clk, reset,
                 output logic [1:0] buffer,
                 output logic bs_flag);
logic [2:0] num_of_ones = 0, num_of_zeroes = 0;
always @(posedge clk, posedge reset)
begin
if (reset)
     begin
     bs_flag <= 0; //область инвертирования
     buffer <= 0;
     end
else if (bs)
     if (inp_seq)
         begin
         num_of_ones <= num_of_ones + 1;
         if (num_of_ones == 3'd4)
         begin
             buffer[1] <= ~inp_seq;
             buffer[0] <= inp_seq;
             bs_flag <= 1;
         end
         else if (bs_flag)
         begin
             if (!buffer) //на предыдущем шаге послан 0
             begin //посл-ть: 01
                 //buffer <= buffer << 1;
                 //buffer[0] <= inp_seq;
                 buffer[1] <= inp_seq;
                 num_of_zeroes <= num_of_zeroes + 1;
                 num_of_ones <= 0;
             end
             else
             begin //посл-ть: 11
                 num_of_zeroes <= 0;
                 //buffer <= {2{inp_seq}};
             end
             //bs_flag <= 0;
         end
         else num_of_zeroes <= 0;
     end
     else //!inp_seq
     begin
         num_of_zeroes <= num_of_zeroes + 1;
         if (num_of_zeroes == 3'd4)
         begin
             buffer[1] <= ~inp_seq;
             buffer[0] <= inp_seq;
             bs_flag <= 1;
         end
         else if (bs_flag)
         begin
             if (buffer[1]) //на предыдущем шаге послана 1
             begin //посл-ть: 10
                 //buffer <= buffer << 1;
                 //buffer[0] <= inp_seq;
                 buffer[1] <= inp_seq;
                 num_of_ones <= num_of_ones + 1;
                 num_of_zeroes <= 0;
             end
             else
             begin //посл-ть: 00
                 buffer <= buffer << 1;
                 buffer[0] <= inp_seq;
                 num_of_ones <= 0;
                 //buffer <= {2{inp_seq}};
             end
             //bs_flag <= 0;
         end
         else num_of_ones <= 0;
     end
else
     begin
     num_of_ones <= 0;
     num_of_zeroes <= 0;
     //bs_flag <= 0;
     buffer <= 0;
     end
end
endmodule
module flop(input logic bs_flag, clk, reset, inp_seq,
         input logic [1:0] buffer,
         output logic stuffed_seq);
always @(posedge clk, posedge reset)
if (reset) stuffed_seq <= 1;
else if (bs_flag)
     stuffed_seq <= buffer[1];
     else stuffed_seq <= inp_seq;
endmodule
module testbench();
logic inp_seq, bs, clk, reset;
wire [1:0] buffer;
bit_stuffing stuff(inp_seq, bs, clk, reset, buffer, bs_flag);
flop ff(bs_flag, clk, reset, inp_seq, buffer, stuffed_seq);
always
begin
     clk = ~clk; #10;
end
initial
begin
     $dumpfile("dump.vcd");
     $dumpvars;

     clk = 1;
     reset = 1;
     inp_seq = 1;
     bs = 0;

     #20 reset = 0;
         bs = 1;
         inp_seq = 0;
     #20 inp_seq = 1;
     #20 inp_seq = 0;
     #20 inp_seq = 0;
     #20 inp_seq = 0;
     #20 inp_seq = 1;
     #20 inp_seq = 1;
     #20 inp_seq = 1;
     #20 inp_seq = 0;
     #20 inp_seq = 1;
     #20 inp_seq = 1;
     #20 inp_seq = 0;
     #20 inp_seq = 0;
     #20 inp_seq = 0;
     #20 inp_seq = 0;
     #20 inp_seq = 0;
     #20 inp_seq = 0;
     #20 inp_seq = 1;
     #20 inp_seq = 1;
     #20 inp_seq = 1;
     #20 inp_seq = 1;
     #20 inp_seq = 1;
     #20 inp_seq = 1;
     #20 inp_seq = 0;
     #20 inp_seq = 0;
     #20 inp_seq = 0;
     #20 inp_seq = 0;
     #20 inp_seq = 0;
     #20 inp_seq = 1;
     #20 inp_seq = 1;
     #20 inp_seq = 1;
     #20 inp_seq = 0;
     #20 inp_seq = 0;
     #20 inp_seq = 0;
     #20 inp_seq = 1;
     #20 inp_seq = 0;
     #20 inp_seq = 1;
     #20 inp_seq = 1;
     #20 inp_seq = 1;
     #20 inp_seq = 1;
     #20 inp_seq = 0;
     #20 inp_seq = 1;
     #20 bs = 0;
     #20 $finish;
end
endmodule