Four_Bit_Counter.vhd

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    09:25:59 23/08/2016
-- Design Name:
-- Module Name:    Four_Bit_Counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Four_Bit_Counter is
Port ( clk          : in STD_LOGIC;
       reset        : in STD_LOGIC;
       UP_DOWN      : in STD_LOGIC;
       LOAD         : in STD_LOGIC;
       AUTO_MANUAL  : in STD_LOGIC;
       TICK         : in STD_LOGIC;
       Value        : in STD_LOGIC_VECTOR(3 downto 0);
       Port_Counter : out STD_LOGIC_VECTOR(3 downto 0));

end Four_Bit_Counter;

architecture Behavioral of Four_Bit_Counter is
-- to store counter before assigning to Port_counter
signal temp: STD_LOGIC_VECTOR(0 to 3);

signal clk_enable: STD_LOGIC;
signal counter_enable: STD_LOGIC;

--for TICK pushbutton
signal sync_r: STD_LOGIC;
signal old_state_r: STD_LOGIC;

begin

    -- asynchronous process for LOAD pushbutton
    process(LOAD) begin
        if (counter_enable = '0' and LOAD = '1') then
            temp <= Value;
        else
            temp <= "0000";
        end if;
    end process;

--    here "sync_r" is the name i gave to the first register (it does metastability synchronization)
--    and old_state_r is the name of the second register (for storing the previous state of the signal
--    to detect edges)
    process (clk) begin
        if rising_edge(clk) then
            sync_r <= TICK;
            old_state_r <= sync_r;
            counter_enable <= sync_r and (not old_state_r);
        end if;
    end process;

    -- Counter Process
    process(clk, reset) begin
        if (rising_edge(clk)) then
            if(reset = '1') then
            --Do reset
                temp <= "0000";
            else
                if (AUTO_MANUAL = '1') then
                --Auto-counting
                    if UP_DOWN = '1' then
                        if temp < "1111" then
                            temp <= temp + 1;
                        else
                            temp <= "1111";
                        end if;
                    else
                        if temp > "0000" then
                            temp <= temp - 1;
                        else
                            temp <= "0000";
                        end if;
                    end if;

                else
                    --Manual Counting

                end if;
            end if;
        end if;
    end process;

    Port_Counter <= temp;

    --clock_enable process
--    process
--        variable count : natural; begin
--        if rising_edge(clk) then
--           clk_enable <= '0';
--           count := count + 1;
--           if count = 100000000/1 then --clock_freq/desired_freq
--              clk_enable <= '1';
--              count := 0;
--           end if;
--        end if;
--    end process;

end Behavioral;